III-V Buffer Layer Selective Epitaxy for Sub-50 nm Trenches
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Solution Overview
Problem
The growth of high-quality crystalline III-V semiconductor materials in sub-50 nm trenches on silicon substrates is challenging due to lattice mismatch, leading to defects such as threading dislocations and twins, which hinder the development of advanced electronic and optoelectronic devices.
Innovation Solution
A method involving selective epitaxial growth of a binary III-V compound buffer layer at a temperature close to the cracking temperature of precursors, followed by a stack of layers with higher growth temperatures, using Metal-Organic Vapor Phase Epitaxy (MOVPE) to form a high mobility channel layer and wide band gap intermediate layer, achieving improved crystallinity and planarity in narrow trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If III-V materials are grown on silicon substrates, then high performance electronic and optoelectronic devices can be enabled, but crystal defects are generated due to lattice mismatch
Solution Approach 1:
A buffer layer comprising a binary III-V compound is introduced as an intermediary between the silicon substrate and the device layers. This buffer layer serves as a mediator that gradually transitions from the silicon lattice structure to the III-V device layer, reducing the abrupt lattice mismatch and thereby minimizing the generation of threading dislocations and other crystal defects.
Solution Approach 2:
The growth temperature is precisely controlled at a first temperature that is equal to or slightly higher than the cracking temperature of the precursors. This specific temperature parameter enables selective epitaxial growth with improved crystallinity and planarity, reducing defect formation while maintaining growth efficiency.
2Productivity
If selective epitaxial growth is performed at high temperature, then growth speed increases, but crystallinity and planarity deteriorate in sub-50 nm trenches
Solution Approach 1:
The growth temperature is optimized to a specific range (equal to or slightly higher than precursor cracking temperature), which balances the competing requirements of growth speed and crystalline quality. This parameter optimization enables high-quality material growth in sub-50 nm trenches without sacrificing productivity.
Solution Approach 2:
Different growth conditions are applied to different parts of the structure: the buffer layer is grown at the optimized first temperature for high crystallinity, while subsequent device layers can be grown at higher temperatures for faster growth rates. This localized quality control allows each layer to be optimized for its specific function.
3Reliability
If buffer layers are used to relieve strain from lattice mismatch, then defect density in device layers is reduced, but manufacturing complexity increases
Solution Approach 1:
The buffer layer acts as a simple intermediary structure that provides strain relief and defect filtering between the silicon substrate and III-V device layers. While it adds one additional layer, the use of selective epitaxial growth with optimized temperature control maintains process simplicity and compatibility with existing manufacturing techniques.
Solution Approach 2:
By controlling the growth temperature at the precursor cracking temperature, the buffer layer can be formed with excellent crystallinity and planarity in a single epitaxial growth step, avoiding the need for multiple complex processing steps and thereby limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in III-V semiconductor devices with reduced defect density and improved crystallinity, as evidenced by Full Width at Half Maximum (FWHM) values less than 700 arcsec measured by X-ray Diffraction, enabling the fabrication of high-performance devices in narrow trenches.
Implementation Method 1
forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor
Implementation Method 2
The stack of layers and the buffer layer are grown selectively by Metal-Organic Vapor Phase Epitaxy (MOVPE)
Implementation Method 3
The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor
Data Source
AI summary
The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.