III-V and CMOS Package Thermal Conduction via Conductive Vias
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Solution Overview
Problem
The integration of Group III-V semiconductor devices, such as GaN, with CMOS devices is hindered by thermal barriers in the interlayer dielectric layers and the interface with the underlying package or printed circuit board, limiting heat removal and maximum power capability.
Innovation Solution
Incorporating conductive vias within the interlayer dielectric layers, conductive contacts from the lower metal layer to the silicon substrate, and using back-side metallization on the CMOS silicon substrate to enhance heat transfer and facilitate the integration of III-V devices with CMOS driver devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If GaN devices are integrated with CMOS devices using standard interlayer dielectric layers, then device integration is achieved, but heat removal capability deteriorates due to thermal barriers in the dielectric layers
Solution Approach 1:
The patent segments the interlayer dielectric structure by introducing conductive vias that divide and bypass the thermal barrier regions, creating multiple heat conduction pathways through the dielectric layers to improve heat removal while maintaining device integration
Solution Approach 2:
The patent introduces an intermediary heat spreader layer between the GaN device and the underlying substrate, which acts as a thermal mediator to enhance heat transfer from the high-power GaN device through the interlayer dielectric structure to the substrate
2Ease of manufacture
If the interface between CMOS device and underlying package or PCB is used for mounting, then device assembly is simplified, but heat removal capability deteriorates due to interface thermal resistance
Solution Approach 1:
The patent extracts the thermal barrier problem by separating the electrical connection function from the thermal management function, using dedicated conductive vias and heat spreader structures that specifically address heat removal without interfering with the simplified assembly interface
Solution Approach 2:
The patent adds a vertical heat conduction dimension by implementing through-silicon vias and heat spreader layers that conduct heat in the vertical direction through the substrate, complementing the horizontal heat flow path and providing additional thermal management capability
3Ease of manufacture
If standard CMOS fabrication processes are used without modifications, then manufacturing simplicity is maintained, but heat removal capability deteriorates due to lack of thermal management structures
Solution Approach 1:
The patent merges thermal management structures with existing CMOS fabrication processes by integrating heat spreader layers and conductive via formation into the standard manufacturing flow, achieving enhanced heat removal without significantly increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased operating speeds and temperatures while improving heat removal from III-V devices, enabling more efficient power handling and integration with CMOS devices.
Implementation Method 1
Incorporating conductive vias within the interlayer dielectric layers, conductive contacts from the lower metal layer to the silicon substrate, and using back-side metallization on the CMOS silicon substrate to enhance heat transfer
Data Source
AI summary
Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate, a plurality of transistors overlying the semiconductor substrate, and an interlayer dielectric layer overlying the plurality of transistors with a metallization layer disposed within the interlayer dielectric layer. The plurality of transistors and the metallization layer form a gate driver circuit. The integrated circuit further includes a plurality of vias disposed through the interlayer dielectric layer, a gate driver electrode coupled to the gate driver circuit, a III-V device electrode overlying and coupled to the gate driver electrode, and a III-V device overlying and coupled to the III-V device electrode.