III-V Source/Drain Contact Structure With Metal Silicide Patterns

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Solution Overview

Problem

Existing semiconductor devices with III-V compound semiconductor layers face challenges in reducing contact resistance between the source/drain structure and the semiconductor layer, which limits the operational performance of the devices.

Innovation Solution

The semiconductor device incorporates a source/drain structure formed with metal silicide patterns and a metal layer disposed on the metal silicide patterns, with a portion of the metal layer located between adjacent metal silicide patterns. This configuration reduces contact resistance and enhances operational performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional source/drain structure is used with III-V compound semiconductor layer, then the device structure is simple, but the contact resistance between source/drain structure and semiconductor layer is high

Engineering Contradiction:
Improvecontact resistanceVSAvoidsource/drain structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain structure employs a composite configuration combining metal silicide patterns with a metal layer, creating a hybrid material system that leverages the low resistivity of metals and the adhesion properties of metal silicides to achieve reduced contact resistance with the III-V compound semiconductor layer

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The source/drain structure is segmented into discrete metal silicide patterns rather than a continuous layer, with the metal layer filling the spaces between them. This segmentation allows optimized electrical contact while reducing overall material usage and enabling better control over contact resistance characteristics

Inventive Principle:
Principle #1Segmentation

2Reliability

If the contact resistance is reduced by modifying source/drain structure, then the operational performance is enhanced, but the manufacturing process complexity increases

Engineering Contradiction:
Improveoperational performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The metal silicide patterns are formed first through selective deposition and silicidation processes, creating predefined contact regions on the III-V compound semiconductor layer. Subsequently, the metal layer is deposited to fill the spaces between these pre-formed patterns, ensuring optimized contact resistance is achieved before final device assembly

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12317565B2Manufacturing method of semiconductor device
Publication Date: 2025.05.27 UNITED MICROELECTRONICS CORP
  • US12317565B2 patent drawing
  • US12317565B2 patent drawing
  • US12317565B2 patent drawing

AI summary

A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.