III-V E-FET Layer Segmentation for Integrated n- and p-Channel HEMTs
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Solution Overview
Problem
Integrated high electron mobility transistor (HEMT) devices face performance reduction due to shared III-V layers with conflicting thicknesses and material concentrations for optimal n-channel and p-channel device performance.
Innovation Solution
The method involves forming an integrated HEMT device with selectively patterned III-V layers, where a lower undoped layer and a first barrier layer are formed over a substrate, and a first doped layer is patterned for the n-channel device. A second barrier layer and second doped layer are then formed for the p-channel device, optimizing the thickness and material concentration of each layer for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a shared III-V layer structure is used for both n-channel and p-channel devices, then device integration is achieved, but optimal performance for both device types cannot be simultaneously obtained due to conflicting thickness and material concentration requirements
Solution Approach 1:
The shared III-V layer is segmented into distinct regions with different thicknesses and material concentrations. The barrier layer is divided into a first portion (thinner) for n-channel devices and a second portion (thicker) for p-channel devices, allowing each device type to have optimized layer characteristics while sharing the same overall structure
Solution Approach 2:
Different portions of the barrier layer are assigned different local properties (thickness and material concentration) according to the specific requirements of underlying device regions. The first portion has lower indium concentration and thinner profile for n-channel optimization, while the second portion has higher indium concentration and thicker profile for p-channel optimization
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a first semiconductor layer overlying a substrate. A first barrier layer is disposed on the first semiconductor layer. A second semiconductor layer overlies and directly contacts the first barrier layer. A second barrier layer directly contacts the first barrier layer. A third semiconductor layer overlies the second barrier layer. A fourth semiconductor layer overlies the third semiconductor layer. Outer sidewalls of the third semiconductor layer, outer sidewalls of the fourth semiconductor layer, and outer sidewalls of the second barrier layer are respectively aligned.