III-V FET Overlapped Extensions Gate Last Process
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Solution Overview
Problem
Conventional self-aligned III-V MOS-HEMTs and MOSFETs face limitations due to underlapping channel structures and strain relaxation issues caused by ion implantation, leading to reduced transconductance and reliability, as well as insufficient diffusion and activation of implanted ions.
Innovation Solution
A method and structure for forming self-aligned overlapped extensions in III-V compound semiconductor-containing heterostructure FETs using a gate last process, which involves forming a doped contact layer, a dielectric layer, and gate spacers to create a T-shaped gate structure with an undoped region below the gate, allowing for effective gate length alignment and minimizing strain relaxation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If ion implantation techniques are used to create overlapped extensions in III-V devices, then overlapped channel structure is achieved, but strain relaxation occurs which degrades transport properties
Solution Approach 1:
The patent applies preliminary action by forming the overlapped extension regions through selective epitaxial growth before gate fabrication, rather than using ion implantation after gate formation. This preliminary structuring allows the channel to be overlapped without subsequent ion implantation that would cause strain relaxation, thus achieving both the desired shape and maintaining transport properties.
2Reliability
If RTA temperature is kept low to prevent strain relaxation, then transport properties are maintained, but ion diffusion and activation become insufficient
Solution Approach 1:
The patent extracts the ion implantation step entirely from the process by using selective epitaxial growth to form doped extension regions. This eliminates the need for RTA processing, removing the conflicting requirements between preventing strain relaxation and achieving sufficient ion diffusion/activation, as doping is achieved during the low-temperature epitaxial growth process itself.
3Reliability
If gate dielectric layer is inserted to reduce gate leakage, then gate leakage is reduced by six to ten orders of magnitude, but transconductance decreases due to larger gate-to-channel separation
Solution Approach 1:
The patent applies parameter changes by using high-k dielectric materials with dielectric constants significantly higher than conventional silicon dioxide. This allows the gate dielectric layer to maintain sufficient electrical insulation (reducing gate leakage) while having a larger dielectric constant compensates for the increased physical thickness, thereby preserving the electric field strength and maintaining transconductance performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned overlapped III-V MOS-HEMTs and MOSFETs with improved transconductance and reliability by avoiding strain relaxation and ensuring sufficient ion diffusion and activation, thus enhancing the performance of III-V semiconductor devices.
Implementation Method 1
forming gate spacers having an upper surface that is substantially flush with the upper surface of the dielectric layer on sidewalls of the gate trench
Implementation Method 2
An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure
Data Source
AI summary
A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one layer; forming a doped contact layer on the III-V compound semiconductor-containing heterostructure; and forming a gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the doped contact layer. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.