III-V Fin Structure Diffusion Barrier for STI Defect Control
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Solution Overview
Problem
The integration of III-V FinFETs on a silicon substrate is challenging due to lattice mismatch, leading to crystalline defects and device performance degradation, particularly during the Aspect Ratio Trapping (ART) technique where interactions between SEG precursors and STI structures cause defects in the STI structures.
Innovation Solution
Coating the STI structures with a diffusion barrier, such as an oxide comprising metal like aluminum or hafnium, to prevent defects and improve the reliability of III-V fin structures by suppressing in-diffusion of doping species and oxygen vacancy formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Aspect Ratio Trapping (ART) technique is used to grow III-V fins on silicon substrate, then non-silicon channels can be realized on silicon substrate, but crystalline defects form in STI structures due to interaction between SEG precursors and STI structures
Solution Approach 1:
A silicon nitride layer is introduced as an intermediary barrier between the STI structures and the III-V fin structure. This layer prevents direct interaction between SEG precursors and STI structures, blocking the formation of crystalline defects while allowing the ART technique to function. The silicon nitride layer is deposited conformally and then patterned to create openings that expose the silicon substrate for fin growth while maintaining coverage over the STI structures.
2Reliability
If diffusion barrier is added to prevent precursor interaction with STI structures, then defect formation is reduced, but process complexity increases
Solution Approach 1:
The silicon nitride layer is applied selectively only where needed - conformally over the STI structures and then patterned to create openings above the active growth regions. This local application approach provides defect protection precisely where precursor interaction occurs while maintaining open pathways for fin growth, avoiding the need to add diffusion barriers throughout the entire structure.
3Ease of manufacture
If III-V materials are grown on silicon substrate, then cost effectiveness is improved compared to using III-V substrates, but large lattice mismatch leads to crystalline defects
Solution Approach 1:
The silicon nitride layer converts the harmful effect of lattice mismatch into a beneficial outcome by providing a protective barrier that prevents the propagation of crystalline defects. While the lattice mismatch between III-V materials and silicon substrate cannot be eliminated, the silicon nitride layer traps potential defects at the STI interface, preventing them from degrading device performance and enabling successful heteroepitaxial growth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diffusion barrier enhances the electrical and structural reliability of III-V fin structures by reducing defects, trap-assisted tunneling leakage, and low-frequency noise, thereby improving device performance and allowing co-integration of III-V and Ge channels.
Implementation Method 1
At least the sidewalls of the STI structures are coated with a diffusion barrier
Implementation Method 2
Oxidation of these doping atoms at the surface of the STI structure leads to the formation of a second type of defects
Data Source
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AI summary
A method of producing a III-V fin structure within a gap of a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, wherein the method further comprises coating said at least two identical STI structures with a diffusion barrier at least on each side wall and wherein said semiconductor substrate is a Si substrate.