III-V FinFETs with Quantum Wells for Leakage Reduction
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Solution Overview
Problem
The growth of high-quality III-V compound semiconductor films on dissimilar substrates is challenging due to lattice constant and thermal expansion coefficient mismatches, which hinders the development of III-V based transistors with high electron or hole mobility.
Innovation Solution
A method for forming fin field-effect transistors (FinFETs) using epitaxially grown III-V compound semiconductor regions with alternating layers of different band gaps, where a buffer layer is optionally used to bridge the lattice constant mismatch between the substrate and the III-V compound semiconductor region, and multiple quantum wells are formed to reduce leakage current and enhance drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If III-V compound semiconductor films are grown on dissimilar substrates, then high electron mobility and drive current are achieved, but lattice constant mismatch and thermal expansion coefficient differences cause poor film quality and manufacturing difficulties
Solution Approach 1:
A buffer layer is introduced as an intermediary between the dissimilar substrate and the III-V compound semiconductor film. This buffer layer has lattice constant and thermal expansion coefficient values that are intermediate between those of the substrate and the III-V compound semiconductor, thereby reducing the mismatch effects and enabling high-quality film growth while preserving the high electron mobility benefits
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including the substrate, buffer layer, and III-V compound semiconductor layers with different band gaps. This composite material approach allows each layer to be optimized for its specific function while working together to achieve both high electron mobility and manufacturing feasibility
2Reliability
If alternating layers of different III-V compound semiconductor materials are formed, then quantum wells are created to reduce leakage current, but device structure and manufacturing process become more complex
Solution Approach 1:
The III-V compound semiconductor region is segmented into alternating layers of different materials (e.g., InGaAs and AlGaAs) with different band gaps. This segmentation creates multiple quantum wells that confine carriers effectively, reducing leakage current. The segmented structure is achieved through sequential epitaxial growth processes
Solution Approach 2:
The patent varies the band gap parameter by using alternating layers of III-V compound semiconductor materials with different compositions and band gaps. This parameter change creates the quantum well potential profiles necessary for carrier confinement and leakage current reduction, while the variations are systematically controlled during epitaxial growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in reduced leakage current and increased drive current of the FinFETs by confining carriers in quantum wells, thereby improving the performance of III-V transistors.
Implementation Method 1
performing an epitaxial growth process to form a III-V compound semiconductor region in the trench
Implementation Method 2
the first and the second plurality of III-V compound semiconductor layers form a plurality of quantum wells
Data Source
AI summary
A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.