III-V FinFET Lattice Mismatch Mitigation

Solution Overview

Problem

Forming CMOS devices with dissimilar active regions using III-V compound materials poses a challenge due to lattice constant mismatches, leading to undesirable defects in epitaxially grown active regions, which degrade device performance.

Innovation Solution

A method involving the formation of semiconductor fins on a substrate using Si, SiGe, or Ge materials and III-V compound materials, where a punch through stopper layer with low lattice mismatch is used to grow epitaxial materials, minimizing defects by sequential epitaxy in a single chamber and selective etching processes to expose and grow dissimilar materials on the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dissimilar semiconductor materials are used for pFET and nFET active regions, then device performance is improved at lower supply voltages, but lattice constant mismatches cause undesirable defects in epitaxially grown regions

Engineering Contradiction:

Improvedevice performanceVSAvoiddefects in epitaxially grown regions

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

A sacrificial intermediate layer is introduced between the substrate and the dissimilar semiconductor materials. This intermediate layer serves as a mediator that accommodates the lattice constant mismatch between different materials (e.g., Si and III-V compounds), allowing epitaxial growth to proceed with minimal defects. The intermediate layer is later removed selectively to release strain and prevent defect propagation in the final device structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The epitaxial growth process is segmented into distinct stages: first growing material on the substrate, then forming and removing the sacrificial intermediate layer, and finally growing the remaining dissimilar materials. This segmentation allows each growth stage to be optimized independently and enables the intermediate layer to fulfill its mediating function without interfering with the final device performance.

Inventive Principle:

Principle #1Segmentation

2Productivity

If optical lithography is used for device scaling, then manufacturing capability is improved, but minimum dimensions are limited by the wavelength of irradiation

Engineering Contradiction:

Improvedevice scaling capabilityVSAvoidminimum dimensions

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

A sacrificial intermediate layer is introduced between the substrate and the dissimilar semiconductor materials. This intermediate layer serves as a mediator that accommodates the lattice constant mismatch between different materials (e.g., Si and III-V compounds), allowing epitaxial growth to proceed with minimal defects. The intermediate layer is later removed selectively to release strain and prevent defect propagation in the final device structure.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The epitaxial growth process is segmented into distinct stages: first growing material on the substrate, then forming and removing the sacrificial intermediate layer, and finally growing the remaining dissimilar materials. This segmentation allows each growth stage to be optimized independently and enables the intermediate layer to fulfill its mediating function without interfering with the final device performance.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in CMOS devices with significantly reduced defects in epitaxially grown active regions, enhancing the performance of FET devices by using dissimilar semiconductor materials for pFET and nFET, thereby improving the overall performance of CMOS devices at lower supply voltages.

Implementation Method 1

removing portions of the insulator layer to form a first cavity and a second cavity

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

growing a first semiconductor material in the first cavity and the second cavity, growing a second semiconductor material on the first semiconductor material

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity

Methodology Applied

Scientific EffectPhotomasking:

Data Source

PatentUS9917089B2III-V semiconductor CMOS FinFET device

Publication Date: 2018.03.13 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A method for forming a semiconductor device comprises forming an insulator layer on a semiconductor substrate, removing portions of the insulator layer to form a first cavity and a second cavity, the first cavity exposing a first portion of the semiconductor substrate an the second cavity exposing a second portion of the semiconductor substrate, growing a first semiconductor material in the first cavity and the second cavity. Growing a second semiconductor material on the first semiconductor material in the first cavity and the second cavity, growing a third semiconductor material on the second semiconductor material in the first cavity and the second cavity. Forming a mask over the third semiconductor material in the first cavity, removing the third semiconductor material from the second cavity to expose the second semiconductor material in the second cavity, and growing a fourth semiconductor material on the second semiconductor material in the second cavity.