III-V Gate Trench Structure for Normally-Off HEMT Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices with III-V compound materials face challenges in enhancing electrical performance and simplifying manufacturing processes, particularly in achieving improved material quality and reduced electrical resistance for III-V compound layers in high electron mobility transistors.
Innovation Solution
A semiconductor device design where a p-type doped III-V compound layer is formed within a trench of a III-V compound barrier layer, with the top surface of the p-type doped layer being substantially coplanar with the barrier layer, reducing electrical resistance and enabling a normally-off transistor configuration, and a manufacturing method involving epitaxial growth to achieve this configuration without additional etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type doped III-V compound layer is formed in a trench of a III-V compound barrier layer, then the electrical performance is improved and material quality is enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the p-type doped III-V compound layer and the III-V compound barrier layer simultaneously during the epitaxial growth process, before subsequent manufacturing steps. This preliminary formation ensures proper material quality and electrical performance while avoiding the need for additional etching processes that would increase manufacturing complexity
Solution Approach 2:
The patent converts the potential harm of etching damage to the III-V compound barrier layer into a benefit by eliminating the etching step entirely. By forming the p-type doped layer in-situ during epitaxial growth, the method avoids the harmful effects of etching while still achieving the desired trench structure and electrical performance
2Reliability
If the top surface of the p-type doped III-V compound layer is made coplanar with the barrier layer, then material quality is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by designing the epitaxial growth process to automatically achieve coplanar surfaces. The p-type doped III-V compound layer and the III-V compound barrier layer are grown simultaneously under controlled conditions that inherently produce coplanar top surfaces, eliminating the need for additional planarization processes and reducing manufacturing precision requirements
3Ease of manufacture
If additional etching processes are used to form the trench, then the gate structure can be defined, but etching damage occurs to the III-V compound barrier layer
Solution Approach 1:
The patent extracts the harmful etching step from the manufacturing process by forming the trench structure through selective epitaxial growth instead. The gate structure is defined by the patterned growth of the p-type doped layer, eliminating the need for separate etching processes and avoiding etching damage to the III-V compound barrier layer
Solution Approach 2:
The patent replaces the mechanical/chemical etching process with an epitaxial growth process to define the gate structure. This substitution uses controlled material deposition instead of material removal, avoiding the harmful effects of etching while achieving the same structural definition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances the material quality and electrical performance of semiconductor devices by reducing resistance and achieving a positive threshold voltage, while simplifying the manufacturing process by avoiding etching damage and ensuring precise layer formation.
Implementation Method 1
A p-type doped III-V compound layer is formed in a trench of a III-V compound barrier layer
Data Source
AI summary
A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.