Monolithic III-V/IV Cascode Driver for Enhancement Mode
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Solution Overview
Problem
Conventional group III-V high electron mobility transistors (HEMTs) are typically depletion mode, making them normally ON, which is undesirable in power applications where enhancement mode functionality is required, and existing solutions require hybrid assemblies with separate dies, precluding monolithic integration of multiple transistors.
Innovation Solution
A power converter with an integrated driver IC for depletion mode group III-V transistors, where a group IV control switch is monolithically integrated into a separate die to cascode with the group III-V transistor, enabling enhancement mode operation and allowing monolithic integration of multiple transistors on a single semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If depletion mode group III-V transistors are used, then high current densities with low resistive losses are achieved, but enhancement mode functionality is lost making the transistors normally ON which is undesirable in power applications
Solution Approach 1:
The patent combines a depletion mode group III-V transistor with a low voltage group IV transistor into a single integrated device structure. The group IV transistor is positioned in series with the group III-V transistor, forming a composite power switch that achieves enhancement mode functionality while maintaining the low resistive losses of the group III-V transistor through monolithic integration on a single semiconductor die
2Ease of operation
If hybrid assemblies with separate dies are used for depletion mode and low voltage switches, then enhancement mode functionality is achieved, but monolithic integration of multiple transistors is precluded
Solution Approach 1:
The patent merges the depletion mode group III-V transistor and the low voltage group IV transistor into a single monolithic integrated circuit on one semiconductor die. This integration eliminates the need for hybrid assemblies with separate dies, reducing parasitic inductances and capacitances while achieving enhancement mode functionality through the cascoded transistor structure
3Ease of operation
If separate dies are used for fabrication of low voltage switches and group III-V HEMTs, then enhancement mode composite power switches are produced, but package size increases and parasitic inductances are increased
Solution Approach 1:
The patent integrates both the low voltage group IV transistor and the depletion mode group III-V transistor on a single semiconductor die, eliminating the need for separate dies and reducing package size. This monolithic integration minimizes parasitic inductances and capacitances by reducing the physical distance and interconnection requirements between the transistor components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the use of low voltage IC technology for the group IV control switch, reducing parasitic inductances and capacitances, minimizing package size, and achieving enhancement mode functionality for depletion mode group III-V transistors, thereby improving power conversion performance.
Implementation Method 1
a group IV control switch is monolithically integrated into a separate die to cascode with the group III-V transistor, enabling enhancement mode operation
Implementation Method 2
Group III-V high electron mobility transistors (HEMTs), such as III-Nitride HEMTs, typically operate using piezoelectric polarization fields to generate a two-dimensional electron gas (2DEG) that allows for high current densities with low resistive losses
Data Source
AI summary
In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.