III-V on IV Contact Stack Layout for Planar Low-Loss Integration
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Solution Overview
Problem
The integration of group III-V and group IV devices is hindered by inaccurate alignment, significant optical and electrical losses, and complexity due to non-planar contacts and residual materials from conventional lift-off techniques, making them incompatible with modern back-end-of-line multi-level metallization schemes.
Innovation Solution
A semiconductor structure is developed with group III-V devices bonded to a group IV substrate using oxygen plasma-assisted direct wafer bonding, followed by patterning and the formation of precursor stacks over the III-V devices, which are then planarized and connected using a dielectric layer and metal liners to facilitate efficient electrical and optical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional lift-off techniques are used to form contacts for group III-V devices, then the contacts can be formed, but residual materials remain that are difficult to clean and the contacts become non-planar, increasing complexity
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer (dielectric material) over the group III-V device before forming the contact structure. This pre-planarization step ensures that subsequent metal layers and interconnect structures can be formed on a planar surface, eliminating the non-planar contact issues caused by conventional lift-off techniques on high-aspect-ratio structures.
Solution Approach 2:
The patent introduces a dielectric planarization layer as an intermediary between the group III-V device and the contact metal layers. This intermediary layer fills the spaces around high-aspect-ratio structures and provides a planar surface for subsequent processing, thereby simplifying the overall contact structure formation while maintaining ease of manufacture.
2Adaptability or versatility
If group III-V devices are separated from group IV devices, then each device type can be optimized independently, but optical losses increase due to separation distance and misalignment
Solution Approach 1:
The patent merges group III-V and group IV devices into a single integrated semiconductor structure. The group III-V device is formed directly on the group IV substrate with shared epitaxial layers and integrated contact structures, eliminating the need for separate device fabrication and subsequent optical coupling. This integration maintains the optical advantages of close proximity while allowing independent optimization of each device type through selective doping and layer composition.
Solution Approach 2:
The patent utilizes vertical layering (another dimension) to integrate both group III-V and group IV devices within the same substrate thickness. By forming different device regions at different vertical positions and using selective etching and doping techniques, the patent achieves three-dimensional integration that reduces horizontal separation distance and improves optical coupling efficiency while maintaining design flexibility.
3Reliability
If gold metal layer is used for contacts, then good electrical conductivity is achieved, but gold acts as a dopant to silicon causing unintended consequences
Solution Approach 1:
The patent extracts gold from the contact metal stack and replaces it with alternative metals such as tungsten, titanium, or nickel. This extraction eliminates the harmful doping effects of gold on the silicon substrate while maintaining good electrical conductivity through the use of these alternative metals, which do not diffuse into or dope the silicon lattice.
Solution Approach 2:
The patent changes the material parameter of the contact metal from gold to alternative metals with different chemical properties. These alternative metals provide comparable or superior electrical conductivity without the unwanted dopant effects, thereby changing the material composition parameter to eliminate harmful interactions with the silicon substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces optical and electrical losses, improves alignment, and enables compatibility with modern metallization schemes, resulting in a more efficient and reliable integration of group III-V and group IV devices with low contact resistance and simplified fabrication.
Implementation Method 1
bonded to a group IV substrate using oxygen plasma-assisted direct wafer bonding
Implementation Method 2
oxygen plasma-assisted direct wafer bonding
Data Source
AI summary
A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.