III-V Charge Trapping Barrier for Fast Nonvolatile Memory
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Solution Overview
Problem
Conventional flash memory devices face challenges in combining long-term charge retention with fast write and erase times due to the trade-off between oxide layer thickness for non-volatility and electron transfer probability.
Innovation Solution
A memory cell design utilizing a charge trapping barrier made of III-V semiconductor material to enable selective passage of charge carriers between the control gate and the floating gate, allowing for lower voltages and faster operations while maintaining non-volatility, with a charge blocking barrier that can be thicker and more sensitive for read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the oxide layer is made thinner to facilitate electron transfer between channel and floating gate, then write and erase speeds improve, but charge retention capability deteriorates
Solution Approach 1:
The patent divides the single oxide layer into two separate oxide layers: a first oxide layer between the channel and floating gate for electron transfer, and a second oxide layer between the control gate and floating gate for charge retention. This segmentation allows each layer to be optimized independently for its specific function, resolving the contradiction between speed and reliability.
2Speed
If high voltage is applied to enable hot-carrier injection for fast charge transfer, then write speed improves, but oxide layer degradation increases
Solution Approach 1:
The patent introduces a charge trapping layer as an intermediary between the channel and floating gate. This layer facilitates electron transfer through trap-assisted tunneling at lower voltages, avoiding the high electric fields that cause oxide layer degradation while maintaining fast charge transfer speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves storage times of up to 10,000 years for non-volatile memory and faster write/erase speeds of less than 100 ns, with potential applications in both non-volatile and semi-volatile memory types, improving upon current DRAM capabilities.
Implementation Method 1
Flash memory typically makes use of one of two mechanisms for the transfer of charge between the channel and the floating gate, namely Fowler-Nordheim tunnelling and hot-carrier injection (HCI). Fowler-Nordheim tunnelling is a quantum mechanical effect relying on the tunnelling of electrons through a potential barrier.
Implementation Method 2
Due to the electrical isolation of the floating gate, which is typically achieved by placement of an oxide layer between the channel and the floating gate, and an oxide layer between the control gate and the floating gate, charge may be held within the floating gate for extremely long periods of time without the risk of charge being removed from the floating gate.
Implementation Method 3
The probability of an electron passing through a barrier is greater for barriers of a smaller width, and thus, in order to facilitate the transfer of electrons between the channel and the floating gate, it is desirable to have as thin a layer of oxide as possible.
Data Source
AI summary
A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.