III-V Mesa Wafer Structure for Fast, Low-Resistance Power Switching
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Solution Overview
Problem
Current semiconductor devices for power electronic applications, such as silicon-based transistors, face limitations in carrying large currents and supporting high voltages with low on-resistance and fast switching times, prompting the need for improved materials and fabrication methods.
Innovation Solution
A method for fabricating semiconductor wafers involves epitaxially growing III-V semiconductor layers on a foreign wafer, forming mesas with insulation layers, and creating a metallization structure with buses to enable efficient transistor formation, including a gate finger, drain finger, and source finger, with the option to reduce the wafer thickness and implement parasitic channel suppression regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon-based transistors are used for power electronic applications, then the devices can be fabricated with established processes, but the current carrying capacity and switching speed are limited
Solution Approach 1:
The patent changes the material parameter from silicon to III-V semiconductor compounds (GaAs, InP, GaN), which fundamentally alters the electrical properties including carrier mobility and saturation velocity, enabling both higher current carrying capacity and faster switching speeds
2Reliability
If III-V semiconductor layers are epitaxially grown on foreign wafers, then the device performance is improved, but the fabrication complexity increases
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the foreign substrate and the III-V semiconductor layers. This buffer layer mediates the lattice mismatch and thermal expansion differences, enabling successful epitaxial growth while simplifying the overall fabrication process
Solution Approach 2:
The patent segments the semiconductor structure into distinct functional layers (buffer layer, active III-V layers, contact layers) that can be grown and processed separately, then integrated into a complete device structure
3Temperature
If the foreign wafer thickness is reduced to improve heat dissipation, then the thermal performance is improved, but the mechanical strength decreases
Solution Approach 1:
The patent creates a composite structure combining the thin foreign wafer with the III-V semiconductor layers and metallization structures. This composite design allows the thin wafer to dissipate heat effectively while the integrated structure provides the necessary mechanical strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by improving current carrying capacity, reducing on-resistance, and increasing switching speed, leading to more efficient power handling and reduced RF losses.
Implementation Method 1
epitaxially growing a III-V semiconductor on a first surface of a foreign wafer
Data Source
Figure 1a~1c
Figure 1d~1e
Figure 2a~2d
AI summary
In an embodiment, a method for fabricating a semiconductor wafer comprises epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface, removing portions of the III-V semiconductor to produce a plurality of mesas comprising the III-V semiconductor arranged on the first surface of the wafer, applying an insulation layer to regions of the wafer arranged between the mesas and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.