III-V Semiconductor Device Metal-III-V Contact Layer
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Solution Overview
Problem
III-V compound semiconductor devices face challenges in reducing resistance in the source/drain extension regions and contact resistance to achieve high-frequency operation, as existing technologies struggle to maximize performance due to high resistance in these areas.
Innovation Solution
The implementation of a III-V compound semiconductor device with a metallic contact layer comprising a metal-III-V semiconductor compound, which is partially or fully embedded in the source/drain regions, and a silicide contact layer embedded in the gate stack structure, along with epitaxial growth and recessed source/drain regions, to reduce external and intrinsic resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal contacts are used on III-V semiconductor source/drain regions, then the device structure is simple, but the contact resistance is high and performance is limited
Solution Approach 1:
The patent applies composite materials by forming a metal-III-V compound semiconductor layer that combines metal atoms with III-V semiconductor atoms. This composite structure creates an intermediate layer between the metal contact and the source/drain region, improving lattice matching and reducing contact resistance while maintaining structural integrity.
Solution Approach 2:
The metal-III-V compound semiconductor layer acts as an intermediary between the metal contact and the III-V semiconductor source/drain region. This intermediate layer facilitates better atomic-level interface matching, reducing misfit dislocations and contact resistance without requiring complex multi-layer structures.
2Reliability
If source/drain regions are extended to reduce resistance, then conductivity improves, but device area increases and scaling is limited
Solution Approach 1:
The patent changes the material parameter of the source/drain region by forming a metal-III-V compound semiconductor layer with different compositional parameters (metal to III-V atom ratio). This allows optimization of electrical conductivity without changing the geometric dimensions, enabling resistance reduction while maintaining compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the total resistance of the device by enhancing conductivity between metal contacts and source/drain regions, thereby improving the performance and frequency capabilities of III-V semiconductor CMOS devices.
Implementation Method 1
annealing at a raised temperature to form a metallic metal-semiconductor compound material
Implementation Method 2
forming a metallic material comprising a metal-III-V semiconductor compound
Implementation Method 3
epitaxial growth and recessed source/drain regions
Data Source
AI summary
A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.