III-V Multi-Junction Photovoltaic Cell on Silicon Substrate
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Solution Overview
Problem
The challenge lies in manufacturing high-efficiency III-V multi-junction photovoltaic cells on silicon substrates, as the lattice parameter mismatch and thermal expansion differences between silicon and III-V materials lead to defects and stress-induced cracking, making it difficult to achieve good crystalline quality and low dislocation density, while existing methods are costly and complex.
Innovation Solution
A buffer layer made of an antimony and aluminum alloy, with the presence of at least one other group V element, such as arsenic, is used to relax stresses and achieve lattice parameter matching, allowing for the deposition of an active heterostructure with adapted alloys like AlGaInAs and GaInAsP, which enables the formation of stacked PN junctions with different band gaps on a silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If III-V photovoltaic cells are manufactured on silicon substrate, then manufacturing cost is reduced and microelectronics know-how is leveraged, but lattice parameter mismatch and thermal expansion differences cause defects and stress-induced cracking
Solution Approach 1:
A buffer layer comprising a first layer of SiGe alloy and a second layer of GaInAsP alloy is introduced between the silicon substrate and the III-V active layers. This intermediary buffer layer gradually transitions the lattice parameter from silicon to the III-V materials, reducing mismatch and preventing defect propagation while maintaining the cost advantage of silicon substrates.
Solution Approach 2:
The buffer layer uses graded composition alloys where the lattice parameter changes gradually from the silicon substrate through the SiGe layer to the GaInAsP layer. This continuous parameter change reduces sudden stress concentrations and minimizes dislocation density, improving crystalline quality while keeping manufacturing costs low.
2Manufacturing precision
If lattice parameter matching is achieved using GaN y(P x As 1-x) 1-y quaternary compounds, then lattice parameter match with silicon substrate is achieved, but minority carrier diffusion length is reduced limiting performance
Solution Approach 1:
Instead of using GaN y(P x As 1-x) 1-y quaternary compounds that achieve lattice matching but reduce carrier diffusion length, the patent uses a buffer layer with SiGe and GaInAsP alloys. This intermediary structure achieves lattice parameter transition without degrading the electronic properties of the active III-V layers, maintaining high energy conversion efficiency.
Solution Approach 2:
The buffer layer is designed with different alloy compositions in different layers: SiGe for lattice matching with silicon substrate and GaInAsP for transitioning to the III-V active layers. Each layer has optimized local composition to fulfill its specific function while preserving overall device performance.
3Manufacturing precision
If metamorphic approach with very thick buffer layers is used, then lattice parameter mismatch is accommodated, but manufacturing process becomes expensive and time-consuming
Solution Approach 1:
The buffer layer is segmented into two distinct layers: a first layer of SiGe alloy and a second layer of GaInAsP alloy. This segmentation allows each layer to be optimized for its specific function and reduces the total thickness required compared to a single thick metamorphic buffer, thereby reducing epitaxial growth time and manufacturing cost.
Solution Approach 2:
The buffer layer uses a composite structure combining SiGe and GaInAsP alloys. This composite approach leverages the advantages of both materials: SiGe for lattice matching with silicon and GaInAsP for transitioning to III-V compositions, achieving effective lattice parameter accommodation in a thinner, faster-to-manufacture structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a low defect density and efficient energy conversion, enabling the production of multi-junction photovoltaic cells with improved efficiency and reduced manufacturing costs, as the buffer layer effectively accommodates lattice parameter mismatches and thermal stresses, allowing for the creation of high-performance photovoltaic cells.
Implementation Method 1
the coefficient of thermal expansion is also very different; this induces the appearance of tensile stresses in epitaxial III-V structures during the cooling phase following growth
Implementation Method 2
a buffer layer of at least ternary type III-V alloy comprising aluminum, antimony and at least one other group V element, deposited by epitaxy above said substrate
Implementation Method 3
multi-junction photovoltaic cells, comprising several PN junctions with different band gaps, stacked and connected in series. This allows better use of the solar spectrum, reducing losses by thermalization
Data Source
Figure 1
Figure 2A~2D
AI summary
A multiple-junction photovoltaic cell comprising: - a substrate (20) of monocrystalline silicon; - a buffer layer (30) of type III-V alloy comprising at least aluminium and antimony, deposited by epitaxy on top of the substrate; and - an active heterostructure deposited by epitaxy on top of the buffer layer, formed from at least two different alloys chosen from among the families AlGaInAs and GaInAsP, having mesh parameters matched to one another and with that of the buffer layer and comprising at least two stacked PN junctions (41, 42, 43) having different forbidden bandwidths. A method for producing such a photovoltaic cell.