III-V Optical Interconnects for CMOS Data Transmission

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Solution Overview

Problem

The increasing size of semiconductor devices leads to higher resistance in interconnects, limiting further performance enhancements due to slower data signal transmission speeds across physical electrical communication structures.

Innovation Solution

The implementation of an optical interconnect using III-V light emission and detection devices with epitaxial material layers directly contacting the semiconductor substrate, replacing traditional electrical communication methods to enhance data transmission speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the dimensions of semiconductor devices are shrunk to improve device performance, then device performance is improved, but the resistance of interconnects increases

Engineering Contradiction:
Improvedevice performanceVSAvoidinterconnect resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent replaces traditional electrical interconnects with optical interconnects using light emission and detection devices. This substitution uses optical fields instead of electrical fields to transmit data signals, eliminating the resistance problem that plagues scaled electrical interconnects while maintaining compatibility with scaled semiconductor devices

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Length of moving object

If the interconnect size is decreased to support device scaling, then device scaling is enabled, but the resistance of interconnects increases

Engineering Contradiction:
Improveinterconnect sizeVSAvoidinterconnect resistance
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent substitutes electrical interconnect transmission with optical interconnect transmission. The optical interconnect uses light to carry data signals between semiconductor devices, bypassing the resistance issue that occurs when electrical interconnect dimensions are reduced for device scaling

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If switching speeds are increased to improve performance, then device performance is improved, but the speed of data signal transmission over interconnects becomes the limiting factor

Engineering Contradiction:
Improveswitching speedVSAvoiddata signal transmission speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent replaces electrical signal transmission with optical signal transmission for data communication between semiconductor devices. This enables data signal transmission speeds to keep pace with increased switching speeds, removing the bottleneck that limits further performance enhancements

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution significantly increases data transmission speed by using optical interconnects, outperforming traditional electrical communication methods and overcoming the limitations of increasing resistance in smaller semiconductor device interconnects.

Implementation Method 1

III-V epitaxial semiconductor material formed using lateral overgrowth

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9726819B2Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth
Publication Date: 2017.08.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9726819B2 patent drawing
  • US9726819B2 patent drawing
  • US9726819B2 patent drawing

AI summary

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.