III-V Pillar on SOI via Segmented Epitaxy

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Solution Overview

Problem

The integration of III-V compound semiconductor materials on silicon substrates is challenging due to lattice constant mismatch, limiting the further improvement of metal oxide semiconductor (MOS) performance beyond traditional scaling limits.

Innovation Solution

A semiconductor-on-insulator (SOI) substrate with a miscut silicon or germanium handle substrate is used, where a trench is formed in the insulator layer, and an III-V compound semiconductor pillar is epitaxially grown within this trench, with a lower portion having a higher defect density and an upper portion with a lower defect density, facilitating direct contact with the handle substrate and surrounding dielectric material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If III-V compound semiconductor materials are integrated on silicon substrates, then electron mobility and device performance are improved, but lattice constant mismatch causes high defect density

Engineering Contradiction:

Improvedevice performanceVSAvoiddefect density

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The III-V compound semiconductor pillar is segmented into distinct regions: a lower portion with higher defect density and an upper portion with lower defect density. This segmentation allows the structure to accommodate lattice mismatch at the bottom while providing high-quality material at the top for device fabrication, effectively resolving the contradiction between integration feasibility and device performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the III-V compound semiconductor pillar are assigned different quality characteristics. The lower portion tolerates higher defect density near the silicon interface, while the upper portion maintains low defect density for active device regions. This local quality differentiation enables successful integration despite overall lattice mismatch.

Inventive Principle:

Principle #3Local quality

2Productivity

If continued scaling of MOSFETs is pursued, then device density is improved, but traditional scaling limits are reached

Engineering Contradiction:

Improvedevice densityVSAvoidperformance improvement

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The invention changes the material parameter from conventional silicon to III-V compound semiconductors with fundamentally different properties, particularly higher electron mobility. This parameter change enables continued performance improvement and device density enhancement beyond the scaling limits of traditional silicon MOSFETs.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If a trench with high aspect ratio is formed in the insulator layer, then III-V compound semiconductor pillar integration is enabled, but manufacturing complexity increases

Engineering Contradiction:

Improveintegration feasibilityVSAvoidprocess complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The insulator layer acts as an intermediary that is selectively removed to form trenches, providing a pathway for III-V compound semiconductor pillar integration while maintaining compatibility with existing silicon processing techniques. This intermediary approach enables complex integration without requiring complete redesign of the manufacturing process.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the effective integration of III-V compound semiconductor materials on silicon substrates, enhancing electron mobility and performance beyond traditional scaling limits for future technology nodes.

Implementation Method 1

An III-V compound semiconductor pillar is then epitaxially grown in the trench. In accordance with the present application, the III-V compound semiconductor pillar comprises a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density.

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9754967B2Structure for integration of an III-V compound semiconductor on SOI

Publication Date: 2017.09.05 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.