Selective Oxidation for III-V Semiconductor Device Isolation
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Solution Overview
Problem
The formation of nanowires on a Si substrate is challenging when crystalline semiconductors are stacked on an insulator, and existing methods are defective in growing single crystal insulator starting layers.
Innovation Solution
A method for fabricating a III-V semiconductor device with selective oxidation, involving a stack of two crystalline semiconductor layers, where one layer is selectively oxidized to form an insulating layer, and a gate structure with spacers is formed around fins to create source and drain regions, followed by the deposition of a high-K dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If crystalline semiconductors are stacked on an insulator to form nanowires, then device isolation is improved, but manufacturing defects increase due to challenges in growing single crystal insulator starting layers
Solution Approach 1:
The patent changes the material parameter from traditional insulator materials (SiO2, Si3N4) to oxide semiconductor materials (In2O3, Ga2O3, ZnO) that can be grown as single crystals on III-V semiconductor layers. This parameter change enables the simultaneous achievement of good device isolation and high manufacturing quality by using materials that are crystallographically compatible and can be epitaxially grown without defects.
2Reliability
If traditional trench isolation structures are used with etched semiconductor surfaces, then device isolation is achieved, but structural integrity deteriorates due to surface damage from etching
Solution Approach 1:
The patent applies preliminary oxidation to the III-V semiconductor layer surface before trench formation. By growing an oxide semiconductor layer in advance, the surface is protected from etching damage, and the oxidation process itself prepares the surface for subsequent device fabrication steps, eliminating the need for damaging etch processes while maintaining isolation effectiveness.
Solution Approach 2:
The oxide semiconductor layer acts as an intermediary between the III-V semiconductor and the trench isolation structure. This intermediate layer protects the III-V surface from direct exposure to etchants, preventing surface damage while still allowing for effective device isolation when the trench is formed and filled with dielectric material.
3Object-generated harmful factors
If oxide layers are grown on III-V semiconductor layers, then electrical leakage is reduced, but process complexity increases due to selective oxidation requirements
Solution Approach 1:
The patent applies selective oxidation only to specific regions where isolation is needed, rather than oxidizing the entire III-V layer. By controlling the oxidation process to occur only in trench regions or specific device areas, the patent achieves effective electrical leakage prevention while minimizing the complexity and impact of the oxidation process on the overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective isolation of semiconductor devices, reducing electrical leakage and improving the structural integrity of the semiconductor device by using a selectively oxidized crystalline semiconductor layer as an insulator, enhancing the fabrication process for III-V semiconductor devices.
Implementation Method 1
selectively oxidizing one of the two crystalline semiconductor layers
Data Source
AI summary
Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.