III-V Semiconductor Annealing Defect Reduction via Encapsulation
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Solution Overview
Problem
High temperature annealing of III-V semiconductor materials on mismatched crystalline substrates leads to defects due to evaporation of Group V materials, causing pitting and erosion of layers, which degrades device performance.
Innovation Solution
Surrounding the III-V semiconductor with a thermally stable material on all sides during annealing, including a capping layer above and a substrate below, to prevent evaporation and maintain a controlled environment, allowing for higher annealing temperatures without surface faceting or decomposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature annealing is performed to reduce defect density, then defect annihilation is improved, but material evaporation and surface decomposition occur
Solution Approach 1:
A capping layer is introduced as an intermediary between the annealing environment and the III-V semiconductor surface. This capping layer prevents direct contact between the semiconductor and the annealing atmosphere, thereby preventing Group V material evaporation while allowing thermal energy to pass through and anneal defects in the semiconductor bulk.
Solution Approach 2:
The patent creates an inert environment by sealing the III-V semiconductor with a capping layer and surrounding it with thermally stable material. This inert environment prevents chemical reactions and material evaporation during high temperature annealing, allowing the semiconductor to be heated to temperatures sufficient for defect annihilation without decomposition.
2Reliability
If annealing temperature is increased to annihilate defects, then defect reduction is improved, but surface faceting and erosion worsen
Solution Approach 1:
The capping layer is deposited on the semiconductor surface before the annealing process begins. This preliminary action protects the surface from faceting and erosion that would otherwise occur during high temperature annealing, while still allowing the annealing treatment to penetrate through the capping layer and reduce bulk defects.
Solution Approach 2:
The capping layer serves as a protective intermediary that decouples the surface integrity from the bulk defect reduction process. It allows the semiconductor to be exposed to high annealing temperatures necessary for defect annihilation while preventing the surface from undergoing faceting or erosion.
3Loss of substance
If thermally stable material is deposited to prevent evaporation, then material loss is reduced, but process complexity increases
Solution Approach 1:
A thin film capping layer is used to prevent material evaporation during annealing. This thin film approach provides effective protection against Group V material loss while minimizing the added structural complexity and maintaining compatibility with standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces defect density and improves the crystalline structure of the III-V semiconductor, enhancing its performance and maintaining the surface integrity for further processing.
Implementation Method 1
Surrounding the III-V semiconductor with a thermally stable material on all sides during annealing, including a capping layer above and a substrate below, to prevent evaporation and maintain a controlled environment
Implementation Method 2
annealing the substantially enclosed semiconductor. In some embodiments a method of reducing defects in epitaxially grown III-V semiconductor material comprises: epitaxially growing a III-V semiconductor comprising indium phosphide, gallium arsenide, gallium nitride or a combination comprising one or more of the foregoing on a silicon substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material comprising silicon oxide in the openings; depositing a capping layer comprising silicon oxide over the semiconductor material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor at a temperature of 700 to 850° C. for a time of 1 to 10 minutes
Data Source
AI summary
A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.