III-V Semiconductor Structure on Silicon Substrate

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Solution Overview

Problem

The growth of high-quality III-V semiconductor material layers, such as gallium nitride, on silicon substrates is often hindered by dislocation defects and slip lines due to lattice mismatch, leading to unsuitable material for semiconductor devices.

Innovation Solution

A semiconductor structure is created with adjacent structured regions on the substrate surface featuring {111} crystal planes, which reduces the density of dislocation defects in the III-V semiconductor material layer, allowing for the growth of high-quality layers suitable for semiconductor devices by using buffer layers and strategic etching to control lattice stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If III-V semiconductor material layers are grown on silicon substrates, then high-performance semiconductor devices can be fabricated, but dislocation defects and slip lines occur due to lattice mismatch

Engineering Contradiction:
Improvequality of III-V semiconductor material layerVSAvoiddislocation defects and slip lines
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The substrate surface is divided into multiple adjacent structured regions with different crystal plane orientations ({111} planes at different angles). This segmentation allows different regions to serve different functions: some regions promote vertical slip line growth away from the device area, while others provide low-defect growth zones for the III-V material layer, thereby reducing overall dislocation density in the semiconductor device region

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate surface are given different local qualities through structuring with specific crystal plane orientations. The structured regions have {111} crystal planes oriented at different angles relative to the substrate normal, creating locally optimized conditions for controlling slip line formation and directing defects away from the semiconductor device fabrication area

Inventive Principle:
Principle #3Local quality

2Reliability

If buffer layers are used to reduce dislocation defects, then material quality improves, but manufacturing process complexity increases

Engineering Contradiction:
Improvequality of III-V semiconductor material layerVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate surface is pre-structured with adjacent structured regions having different crystal plane orientations before III-V material layer growth. This preliminary structuring of the substrate creates inherent conditions that guide slip line formation and defect distribution during subsequent epitaxial growth, eliminating the need for complex multi-layer buffer structures and reducing overall process complexity

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a significant reduction of dislocation defects, enabling the fabrication of semiconductor devices with improved performance by minimizing lattice mismatch-induced stress and optimizing the growth of III-V semiconductor materials.

Implementation Method 1

The growth of, for example, gallium nitride (GaN) on silicon (Si) may often result in low-quality GaN layers

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS8779440B2Semiconductor structure and a method of forming the same
Publication Date: 2014.07.15 INFINEON TECHNOLOGIES AG
  • US8779440B2 patent drawing
  • US8779440B2 patent drawing
  • US8779440B2 patent drawing

AI summary

Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.