III-V/Si CMOS Die Stacking for Complementary Power and Logic Circuits
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Solution Overview
Problem
GaN p-type transistors have low p-type mobility, making high-voltage GaN complementary device circuits impractical, while Si CMOS circuits offer low power efficiency for power amplifiers and high-density logic circuits.
Innovation Solution
A heterogenous integration scheme is employed, where III-V n-type transistors with high mobility are formed on a (111) substrate and stacked with CMOS die containing both p-type and n-type transistors on a (100) substrate, utilizing passive devices in the III-V die to replace p-type transistors and direct connections for functional circuits, with reduced interconnection lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If GaN p-type transistors are used in high-voltage circuits, then device integration is attempted, but p-type mobility is too low making complementary device circuits impractical
Solution Approach 1:
The patent segments the complementary device functions by placing n-type transistors on III-V die and p-type transistors on separate CMOS die. This physical segmentation allows each transistor type to operate on its optimal substrate without being constrained by the limitations of creating low-mobility p-type transistors on III-V materials.
Solution Approach 2:
The patent introduces passive devices (such as resistors, capacitors, and inductors) formed on the III-V die as intermediaries to replace the function of p-type transistors. These passive devices act as mediators that enable complementary circuit functionality without requiring low-mobility p-type GaN transistors.
2Productivity
If Si CMOS circuits are used for power amplifiers, then high-density logic circuits are achieved, but power efficiency is very low
Solution Approach 1:
The patent applies local quality by using III-V n-type transistors specifically for power amplifier functions where high power efficiency is critical, while using Si CMOS for logic circuits where high density is important. This localized optimization ensures each circuit type operates on the most suitable substrate for its specific function.
Solution Approach 2:
The patent merges III-V die containing n-type power devices with CMOS die containing p-type logic devices through heterogenous integration. This combination creates a unified system that achieves both high power efficiency in the power amplifier section and high density in the logic section, eliminating the trade-off between these two requirements.
3Adaptability or versatility
If heterogenous integration is used to replace p-type transistors with passive devices, then functional circuits are achieved, but device complexity increases
Solution Approach 1:
The patent makes the III-V die universal by forming both active n-type transistors and passive devices on the same die. This multi-functionality allows a single die to provide both power switching functions and circuit control functions, reducing the need for additional separate components and interconnections despite the heterogenous integration approach.
Data Source
AI summary
A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.