III-V/Si CMOS Die Stacking for High-Efficiency RF Power Circuits
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Solution Overview
Problem
GaN p-type transistors have low p-type mobility, making high-voltage GaN complementary device circuits impractical, while Si CMOS circuits are suitable for low power consumption and high-density logic circuits but have low power-efficiency power amplifiers.
Innovation Solution
A heterogenous integration scheme is employed, where III-V n-type transistors with high mobility are formed on a (111) substrate and stacked with CMOS die containing both p-type and n-type transistors on a (100) substrate, utilizing passive devices in the III-V die to replace p-type transistors and connecting them through interconnections to form functional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If p-type GaN transistors are manufactured, then high-voltage GaN complementary device circuits can be formed, but p-type mobility is much lower than n-type mobility making it impractical
Solution Approach 1:
The patent divides the complementary device circuit into separate III-V die and Si CMOS die. The III-V die contains only n-type transistors while the Si CMOS die contains both p-type and n-type transistors. This segmentation allows each die to be optimized for its specific function, avoiding the need to manufacture low-mobility p-type GaN transistors while still achieving complementary device circuit functionality through heterogenous integration.
Solution Approach 2:
The patent uses passive devices (such as resistors, capacitors, and inductors) formed in the III-V die as intermediaries to replace the function of p-type transistors. These passive devices enable the III-V n-type transistors to work with Si CMOS p-type transistors to form complementary logic circuits, thereby achieving high-voltage complementary device circuits without requiring p-type GaN transistors.
2Use of energy by moving object
If Si CMOS circuits are used for low power consumption and high-density logic circuits, then excellent transistor characteristics are achieved, but power amplifier power-efficiency becomes very low
Solution Approach 1:
The patent applies local quality by using different semiconductor materials for different functional regions. Si CMOS circuits are used for low-power logic and control functions where low power consumption is critical, while III-V n-type transistors are used specifically for power amplifier functions where high power-efficiency is required. This localized material assignment allows each region to operate at its optimal efficiency point.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional heterogenous integration architecture. By stacking the III-V die and Si CMOS die vertically and using through-silicon vias for interconnection, the patent enables high-power-efficiency RF power amplifiers to be directly connected to low-power logic circuits, achieving both high power-efficiency and low power consumption in different functional dimensions of the same integrated system.
Data Source
AI summary
A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.