III-V Source/Drain Silicide Layout for Lower Contact Resistance
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Solution Overview
Problem
Existing semiconductor devices with III-V compound semiconductor layers face challenges in reducing contact resistance between the source/drain structure and the III-V compound semiconductor layer, which affects the operational performance of transistors.
Innovation Solution
A source/drain structure is formed with metal silicide patterns and a metal layer disposed on the metal silicide patterns, with a portion of the metal layer located between adjacent silicide patterns, and an annealing process is used to form these patterns, along with n-type semiconductor regions to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional source/drain structure is formed without metal layer between silicide patterns, then the manufacturing process is simpler, but the contact resistance between source/drain structure and III-V compound semiconductor layer is high
Solution Approach 1:
The source/drain structure is segmented into discrete metal silicide patterns rather than a continuous structure. This segmentation allows metal layers to be strategically positioned between adjacent silicide patterns, creating multiple contact pathways that reduce overall contact resistance while maintaining manufacturing feasibility through patterned deposition processes
Solution Approach 2:
A metal layer is introduced as an intermediary between the metal silicide patterns and the III-V compound semiconductor layer. This intermediate metal layer serves as a conductive bridge that reduces contact resistance by providing a low-resistance pathway for carrier transport between the silicide contact and the semiconductor channel
2Reliability
If annealing process is used to form metal silicide patterns, then the electrical performance is improved, but the process complexity and manufacturing steps increase
Solution Approach 1:
The annealing process is merged with existing manufacturing steps by performing it in-situ within the semiconductor fabrication chamber. This integration allows the silicide formation and metal layer processing to be combined in a single workflow, reducing the need for separate processing equipment and minimizing additional process complexity while achieving the desired electrical performance
3Reliability
If metal layer is disposed between adjacent metal silicide patterns, then contact resistance is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The metal silicide patterns are formed first as a preliminary structure before depositing the metal layer between them. This preliminary action establishes well-defined pattern boundaries and contact locations, providing a template that guides subsequent metal layer deposition and ensures precise positioning without requiring complex real-time alignment processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces contact resistance and enhances the operational performance of semiconductor devices by minimizing nitrogen vacancies and maintaining lattice integrity, thereby improving electrical performance and process stability.
Implementation Method 1
An annealing process is performed, and at least a part of each of the metal patterns and a part of the silicon layer are converted into the metal silicide pattern by the annealing process
Data Source
AI summary
A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.