III-V Silicon Optoelectronic Coupling With External Heater Layout

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Solution Overview

Problem

Conventional chip bonding processes for integrating III-V semiconductor based electro-optical devices with silicon-on-insulator platforms suffer from high optical coupling losses and low yield due to alignment difficulties and the negative impact of heaters on device performance.

Innovation Solution

An optoelectronic device with a silicon-on-insulator platform and a III-V semiconductor based device that includes a heater with electrical traces connected to contact pads on the platform, allowing for efficient heating without interfering with electro-optically active components, and a method for manufacturing this device using micro-transfer printing to ensure accurate alignment and separate heater fabrication processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a heater is integrated into the III-V semiconductor device coupon, then the operating wavelength can be adjusted, but the real estate on the device is reduced and device performance deteriorates

Engineering Contradiction:
Improvewavelength adjustment capabilityVSAvoiddevice real estate
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The heater is extracted from the III-V semiconductor device coupon and relocated to the silicon carrier. This allows the heater functionality to be maintained while preserving the limited real estate on the III-V device coupon for electro-optically active components.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The silicon carrier acts as an intermediary platform that hosts both the III-V semiconductor device coupon and the heater. This mediator structure enables wavelength adjustment while keeping the heater separate from the III-V device components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a heater is integrated into the III-V semiconductor device coupon, then the operating wavelength can be adjusted, but the speed and bandwidth of the EAM are reduced

Engineering Contradiction:
Improvewavelength adjustment capabilityVSAvoidEAM operating speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The heater is extracted from proximity to the electro-optically active components, placing it on the silicon carrier instead. This separation prevents the heater from interfering with the EAM electrodes and maintains high operating speed and bandwidth.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The silicon carrier serves as an intermediary that provides thermal management functionality without allowing the heater to directly interfere with the high-speed electro-optical modulation processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional flip-chip bonding is used to integrate III-V devices with SOI platforms, then the devices can be combined, but optical coupling losses increase and alignment precision deteriorates

Engineering Contradiction:
Improvedevice integrationVSAvoidoptical coupling loss
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The waveguide alignment is predetermined during the fabrication of the III-V device coupon on the silicon carrier, before the actual bonding process. This preliminary alignment action ensures precise optical coupling without requiring complex real-time alignment during bonding.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional flip-chip bonding with a direct bonding approach where the III-V device coupon is bonded face-up to the silicon carrier. This substitution eliminates the need for flipping and complex alignment mechanisms, reducing optical coupling losses.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Ease of manufacture

If conventional flip-chip bonding is used to integrate III-V devices with SOI platforms, then the devices can be combined, but manufacturing yield deteriorates

Engineering Contradiction:
Improvedevice integrationVSAvoidmanufacturing yield
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The III-V device coupon is pre-fabricated with predetermined waveguide alignment on the silicon carrier before bonding to the SOI platform. This preliminary preparation reduces alignment difficulties during the final bonding step, thereby improving manufacturing yield.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the complex flip-chip bonding process with a simplified direct bonding process. This substitution reduces process complexity and alignment difficulties, leading to improved manufacturing yield.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution reduces optical coupling losses, increases device reliability, and preserves real estate on the III-V semiconductor device while maintaining high speed and bandwidth, addressing the limitations of conventional methods.

Implementation Method 1

the III-V semiconductor based device includes a heater and one or more electrical traces, connected to the heater

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

For III-V semiconductors, it is known that their bandgap varies with temperature. As the temperature increases, the bandgap typically becomes smaller and therefore the corresponding operating wavelength becomes longer (red shifting)

Methodology Applied
Scientific EffectBandgap variation with temperature:

Implementation Method 3

the one or more electrical traces extend from the III-V semiconductor based device to respective contact pads on the silicon-on-insulator platform

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 4

a silicon waveguide located within a silicon device layer of the platform... and including a III-V semiconductor based waveguide, coupled to the silicon waveguide

Methodology Applied
Scientific EffectOptical waveguide transmission: Waveguide (optics)

Data Source

PatentUS12197050B2Integrated III-V / silicon optoelectronic device and method of manufacture thereof
Publication Date: 2025.01.14 ROCKLEY PHOTONICS LTD
  • US12197050B2 patent drawing
  • US12197050B2 patent drawing
  • US12197050B2 patent drawing

AI summary

An optoelectronic device. The optoelectronic device comprising: a silicon-on-insulator platform, including: a silicon waveguide located within a silicon device layer of the platform, a substrate, and an insulator layer between the substrate and the silicon device layer; and a III-V semiconductor based device, located within a cavity of the silicon-on-insulator platform and including a III-V semiconductor based waveguide, coupled to the silicon waveguide; wherein the III-V semiconductor based device includes a heater and one or more electrical traces, connected to the heater, wherein the one or more electrical traces extend from the III-V semiconductor based device to respective contact pads on the silicon-on-insulator platform.