III-V on Silicon Integration via Trench Confinement
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Solution Overview
Problem
The integration of III-V semiconductor devices on silicon substrates is challenging due to lattice mismatch, leading to defects and high background doping levels, which affect device performance and cost-effectiveness, especially for high-frequency radio frequency applications.
Innovation Solution
A method involving epitaxial growth of III-V structures on a silicon substrate using a dielectric trench to confine defects, followed by selective etching of a sacrificial layer to form a cavity, allowing for the growth of defect-free and low-doping III-V devices with reduced parasitic capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If III-V materials are grown on silicon substrates, then cost is reduced and scalability is improved, but lattice mismatch causes defects and high background doping levels
Solution Approach 1:
The structure is segmented into distinct regions: a silicon substrate, a buffer layer, and III-V device layers. The buffer layer acts as an intermediate segment that separates the silicon substrate from the III-V materials, isolating the lattice mismatch effects to the buffer region while preserving device quality in the III-V layers.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the silicon substrate and the III-V device layers. This buffer layer mediates the lattice mismatch by providing a transition zone that accommodates the crystal structure differences, preventing defects from propagating into the device region while enabling growth on silicon substrates.
2Productivity
If III-V materials are grown on silicon substrates, then production capacity is improved, but background doping level increases causing leakage paths
Solution Approach 1:
The harmful background doping effect is extracted and confined to the buffer layer region. By separating the buffer function from the device function, the patent removes the source of background doping from the active device region, allowing high-capacity production on silicon while preventing leakage paths in the final device structure.
3Reliability
If small size-III-V wafers are used, then device performance is maintained, but cost increases significantly
Solution Approach 1:
The substrate parameter is changed from small III-V wafers to large silicon substrates. This parameter change enables scalable production and cost reduction while the buffer layer technology maintains the device performance that would otherwise require expensive small wafers, effectively decoupling substrate size from device quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the monolithic integration of high-electron mobility III-V devices on silicon substrates with low defectivity and background doping, facilitating high-frequency performance at a lower cost while minimizing parasitic capacitive coupling.
Implementation Method 1
Initiating growth of a first III-V structure in the trench, thereby forming a bottom part of the first III-V structure inside the trench
Implementation Method 2
Contacting the sacrificial second III-V structure with the liquid etching medium, thereby selectively etching the sacrificial second III-V structure with respect to the first III-V structure and the bottom layer, thereby forming a cavity
Data Source
AI summary
A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.