III-V Semiconductor Subfin Leakage Reduction
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Solution Overview
Problem
Non-planar semiconductor devices, such as FINFETs, face challenges with subfin leakage due to lattice mismatch and chemical interactions between III-V semiconductor alloys and trench dielectric materials, which hinder the formation of high-quality epitaxial layers and increase defects, limiting the effectiveness of conduction band offset in preventing leakage.
Innovation Solution
The use of III-V semiconductor alloys with tailored compositions to minimize lattice mismatch and reduce chemical interactions, allowing for high-quality deposition of subfin regions and channels with a significant conduction band offset, thereby reducing subfin leakage by forming subfin regions with alloys like InAlGaAs and channels with InGaAs, ensuring a sharp transition and limiting leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V semiconductor alloys are used in subfin regions to prevent subfin leakage, then conduction band offset is improved, but lattice mismatch and chemical interactions with trench dielectric increase defects and reduce epitaxial quality
Solution Approach 1:
The patent introduces an intermediary layer between the III-V semiconductor alloy and the silicon substrate/trench dielectric. This intermediary layer acts as a buffer that reduces direct chemical interactions and mitigates lattice mismatch, thereby preventing defect formation while maintaining the conduction band offset benefits of the III-V alloy subfin region
Solution Approach 2:
The patent modifies the compositional parameters of the III-V semiconductor alloy (varying the ratios of group III elements like Al, Ga, In and group V elements like As, Sb) to optimize both the conduction band offset for leakage prevention and the lattice matching with underlying layers, thereby resolving the contradiction between reliability and manufacturing precision
2Reliability
If dopant diffusion is used to create barriers against subfin leakage, then leakage containment is improved, but Debye lengths limit the abruptness of the barrier
Solution Approach 1:
The patent extracts the dopant diffusion process and replaces it with a material-based barrier approach using III-V semiconductor alloys with appropriate band structures. This eliminates the fundamental limitation of Debye length on barrier abruptness by creating a physical heterojunction barrier instead of relying on gradual dopant concentration transitions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of non-planar semiconductor devices with reduced subfin leakage, achieving high-quality epitaxial growth and improved electrical performance by maintaining a sharp transition between the subfin region and channel, enhancing the device's ability to turn ON and OFF effectively.
Implementation Method 1
a second III-V semiconductor alloy on the first III-V semiconductor alloy; wherein: the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy
Data Source
AI summary
Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.