III-V Transistor Source Drain Resistance Reduction
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Solution Overview
Problem
III-V compound semiconductor transistors face high source and drain resistance due to the wide bandgap and high resistivity of the etch stop layer, which adversely affects the drive current.
Innovation Solution
A highly doped semiconductor layer is formed over the channel layer, with a gate dielectric penetrating through and contacting the sidewall of the doped layer, and a gate electrode is placed on the bottom portion of the gate dielectric, eliminating the need for a high resistance etch stop layer and reducing source and drain resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etch stop layer with wide bandgap is used to form recesses for the gate, then the gate can be properly positioned, but the source and drain resistance becomes high
Solution Approach 1:
The patent removes the etch stop layer (InP layer) from the transistor structure entirely. Instead of using it to form recesses, the gate is formed by etching through the contact layer and barrier layers directly, eliminating the high resistance path that the etch stop layer created between the metal source/drain and channel layer.
Solution Approach 2:
The patent changes the doping concentration parameter of the contact layer from lightly-doped to highly-doped (e.g., 1×10^18 to 1×10^20 atoms/cm³), which dramatically reduces the resistivity of the contact layer and eliminates the high source/drain resistance problem that existed when the etch stop layer was present.
2Productivity
If III-V compound semiconductors are used to form NMOS transistors, then electron mobility and drive current are high, but manufacturing cost increases
Solution Approach 1:
The patent uses III-V compound semiconductor layers (InGaAs contact layer, InAlAs barrier layers, InP substrate) to form both NMOS and PMOS transistors on the same substrate. The same material system provides high electron mobility for NMOS and, when appropriately doped, high hole mobility for PMOS, eliminating the need for separate material systems and reducing manufacturing complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces source and drain resistances, thereby increasing the drive current of the transistor.
Implementation Method 1
A highly doped semiconductor layer is formed over the channel layer
Data Source
AI summary
An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode.