III-V Transistors in Silicon CMOS Stack for 1 THz Frequency
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Solution Overview
Problem
Silicon-based transistors are limited in maximum oscillation frequency due to fundamental electron and hole transport limitations, restricting data transmission efficiency and rate over waveguides.
Innovation Solution
Integration of III-V, III-nitride, or antimonide transistors with silicon CMOS devices, where III-V transistors are monolithically integrated in the upper metal layers of the silicon CMOS device or fabricated as chiplets and attached to the back end stack, allowing for higher carrier mobility and lower intrinsic gate capacitance, thus enhancing data transfer speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon-based transistors are used, then manufacturing compatibility and ease of manufacture are maintained, but maximum oscillation frequency and data transmission rate are limited
Solution Approach 1:
The device is divided into two separate semiconductor layers: a first semiconductor layer (silicon CMOS) and a second semiconductor layer (III-V material). Each layer is optimized independently - the silicon layer for manufacturing compatibility and the III-V layer for high frequency performance. This segmentation allows both contradictory requirements to be satisfied in their respective domains.
Solution Approach 2:
The patent combines silicon-based CMOS technology with III-V semiconductor materials to create a composite structure. The silicon provides mature manufacturing processes and reliability, while the III-V material contributes high electron mobility and low capacitance for achieving 1 THz oscillation frequencies. This composite approach resolves the contradiction between ease of manufacture and high speed performance.
2Speed
If III-V transistors are integrated, then maximum oscillation frequency and data rate are increased, but device complexity and integration difficulty increase
Solution Approach 1:
By segmenting the device into separate semiconductor layers with distinct functions, the integration complexity is managed. The III-V layer is placed specifically in the upper metal layers where high frequency performance is needed, while the silicon CMOS layer maintains standard manufacturing processes. This spatial segmentation reduces the overall integration complexity compared to fully homogenous high-frequency designs.
Solution Approach 2:
The patent integrates III-V transistors in the vertical dimension by placing them in the upper metal layers above the silicon CMOS substrate. This vertical stacking approach allows high frequency functionality to be added without significantly increasing the lateral footprint or complicating the planar manufacturing process, thus managing device complexity while achieving high performance.
3Productivity
If III-V transistors are positioned close to package substrate, then data transmission efficiency and rate are improved, but manufacturing and assembly difficulty increase
Solution Approach 1:
The patent merges the III-V transistor layer with the silicon CMOS back-end stack in a monolithic integrated structure. The III-V layer is integrated directly into the upper metal layers of the CMOS device, combining the high frequency transistors with the transmission interface in a single integrated component. This merging eliminates the need for separate assembly steps and reduces manufacturing difficulty while achieving optimal positioning for high data transmission rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the maximum oscillation frequency to approximately 1 THz or higher, enabling improved data volumes and rates over waveguides with minimal losses by positioning III-V transistors close to the package substrate.
Implementation Method 1
III-V, III-nitride, and antimonide material systems have higher electron mobilities, lower electron effective mass, and lower intrinsic gate capacitance compared to silicon based transistors
Implementation Method 2
III-V, III-nitride, and antimonide material systems have higher electron mobilities, lower electron effective mass, and lower intrinsic gate capacitance compared to silicon based transistors
Implementation Method 3
III-V, III-nitride, and antimonide material systems have higher electron mobilities, lower electron effective mass, and lower intrinsic gate capacitance compared to silicon based transistors
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.