III-V and CMOS Stacking With Conductive Interlayer for Higher Density
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Solution Overview
Problem
Existing monolithic integration methods for CMOS and III-V devices face device density limits and inefficiencies due to the need for top-side emission or detection, leading to trade-offs between current injection and light transmission, and restricted design requirements.
Innovation Solution
Forming an electrically conductive interlayer between a partially processed CMOS device layer and a III-V device layer, allowing the III-V device to be located below the CMOS layer, reducing contact resistance and increasing device density, and enabling more flexible back-end interconnect design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If III-V devices are integrated side-by-side with CMOS devices in existing monolithic processes, then device fabrication can proceed with standard top-down process steps, but device density is limited because III-V and CMOS devices cannot occupy the same area from a plan-view perspective
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side layout to a three-dimensional stacked configuration where III-V devices are positioned beneath the CMOS device layer. This vertical integration allows both device types to occupy overlapping footprint areas, effectively doubling the space utilization and increasing device density without compromising fabrication process compatibility
Solution Approach 2:
The patent implements a nested structure where the III-V device layer is embedded within the overall device stack beneath the CMOS layer. The III-V devices are integrated into the substrate region, allowing the CMOS layer to be formed above them, creating a compact nested arrangement that maximizes area efficiency
2Illumination intensity
If III-V optoelectronic devices are designed for top-side emission, then light can be efficiently emitted from the device, but contact metallization requires openings (windows) that create trade-offs between current injection efficiency and light transmission
Solution Approach 1:
The patent inverts the conventional top-side emission architecture by implementing bottom-side emission through the substrate. Light is emitted from the III-V device through the substrate rather than through the contact metallization, eliminating the need for metallization windows and allowing continuous metallization layers for optimal current injection
Solution Approach 2:
The patent extracts the light emission function from the contact metallization region and relocates it to the substrate region. This separation allows the contact metallization to serve its electrical function continuously while light transmission occurs through a different pathway via the substrate
3Illumination intensity
If back-end interconnects are routed around LED emission areas to avoid blocking light, then light transmission is maintained, but interconnect routing complexity increases and device layout flexibility is restricted
Solution Approach 1:
The patent inverts the light emission direction to the bottom side through the substrate, which removes the constraint that forced interconnects to route around emission areas. With bottom-side emission, interconnects can be routed freely on the top side without blocking light paths, significantly simplifying interconnect design and improving layout flexibility
Data Source
AI summary
A method of fabricating a semiconductor device (200) is described. According to a described embodiment, the method comprises: (i) forming a III-V semiconductor material layer (206) comprising a substrate layer (208) and a device layer (210) attached to the substrate layer (208); and (ii) forming an electrically conductive interlayer (228) to the device layer (210) prior to bonding the electrically conductive interlayer (228) to a partially processed CMOS device layer (204) having at least one transistor (205).