Group III-V Device Emulation Calibration for Trap Location Prediction
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Solution Overview
Problem
During the fabrication of Group III-V semiconductor devices, traps form due to lattice and thermal mismatches, leading to degradation in electrical performance. Existing simulation technologies, such as TCAD, struggle to accurately predict trap locations and their impact on device performance, resulting in discrepancies between emulated and actual device characteristics.
Innovation Solution
A calibration method for emulating Group III-V semiconductor devices involves establishing a process emulation program based on actual process flows, performing actual tape-outs, and comparing emulated and actual electrical performances. By identifying failure locations and inserting traps in the emulated device, the program is calibrated to match actual device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing simulation technologies (TCAD) are used to predict trap locations and device performance, then process development time is reduced, but prediction accuracy deteriorates due to discrepancies between emulated and actual device characteristics
Solution Approach 1:
The patent modifies simulation parameters by introducing effective density of states and mobility degradation models that account for trap effects. These parameter changes enable the simulator to accurately predict device characteristics including subthreshold swing and on-current, resolving the discrepancy between emulated and actual device performance while maintaining reduced development time
Solution Approach 2:
The patent introduces an intermediary calibration process that bridges the gap between TCAD simulation and actual device behavior. By using extracted device parameters from measurements to adjust simulation models, the system achieves accurate prediction of trap locations and device performance without requiring extensive trial production
2Measurement precision
If trial production and physical characterization are performed to evaluate device performance, then measurement accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent creates a virtual copy of the device through calibrated TCAD simulation that accurately reproduces actual device behavior. This digital twin allows evaluation of device performance and trap locations without requiring physical fabrication, eliminating the need for costly trial production while maintaining measurement accuracy through parameter extraction and model calibration
3Productivity
If process emulation is performed without calibration, then simulation speed is maintained, but emulation accuracy deteriorates due to inability to predict trap locations
Solution Approach 1:
The patent performs preliminary calibration by extracting device parameters from measurements and using them to configure the simulation model before actual device emulation. This preliminary action establishes accurate effective density of states and mobility degradation parameters, enabling the simulator to accurately predict trap locations and device characteristics while maintaining computational efficiency
Data Source
AI summary
A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.