III-V/Si CMOS Die Stacking for High-Voltage Power Amplifiers
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Solution Overview
Problem
The development of high-voltage GaN complementary device circuits is impractical due to low p-type mobility in GaN transistors, while Si CMOS circuits face low power efficiency in power amplifiers, necessitating a solution that combines the high power efficiency of GaN n-type transistors with the low-voltage capabilities of Si CMOS technology.
Innovation Solution
A heterogeneous integration scheme is employed, where III-V n-type transistors are formed on a (111) substrate for high-voltage applications and CMOS transistors on a (100) substrate for low-voltage operations, with interconnections between the two to create a stacked package that reduces electrical path lengths, leveraging passive devices in the III-V die to replace p-type transistors and directly connecting III-V n-type transistors with CMOS p-type transistors for functional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If p-type GaN transistors are manufactured for high-voltage applications, then high-voltage capability is achieved, but power efficiency deteriorates due to low p-type mobility
Solution Approach 1:
The patent divides the complementary transistor pair into separate materials: n-type GaN transistors for high-voltage switching and p-type Si CMOS transistors for low-voltage control. This segmentation allows each transistor type to operate in its optimal material system, achieving both high-voltage capability and high power efficiency that cannot be obtained in a single GaN-based complementary circuit.
Solution Approach 2:
The patent creates a hybrid CMOS-GaN integrated circuit combining Si CMOS and GaN technologies. The composite structure integrates n-type GaN transistors (providing high-voltage capability and high power efficiency) with p-type Si CMOS transistors (providing low-voltage control), forming a complementary device circuit that overcomes the limitations of single-material systems.
2Stress or pressure
If Si CMOS circuits are used for power amplifiers, then low-voltage control is achieved, but power efficiency deteriorates
Solution Approach 1:
The patent segments the power amplifier function into two parts: low-voltage control signals are generated by Si CMOS circuits, while high-voltage power switching is performed by GaN transistors. This functional segmentation allows Si CMOS to excel at low-voltage control while GaN handles the power-efficient high-voltage switching operations.
Solution Approach 2:
The heterogeneous integrated circuit creates a universal platform where Si CMOS provides low-voltage control functionality and GaN provides high-voltage power amplification functionality. This multi-functional integration allows a single chip to perform both control and power amplification with optimal efficiency at each voltage level.
3Adaptability or versatility
If III-V and CMOS dies are bonded side-by-side, then integration is achieved, but electrical path lengths increase causing higher latency
Solution Approach 1:
The patent transitions from planar side-by-side bonding to three-dimensional stacked bonding, placing the Gan die directly over the Si CMOS die. This vertical stacking in the third dimension dramatically shortens the electrical interconnection paths between n-type GaN transistors and p-type Si CMOS transistors, reducing latency while maintaining full integration capability.
Solution Approach 2:
The patent implements a nested structure where the GaN die is stacked directly on top of the Si CMOS die, with interconnections made through vertical vias. This nesting arrangement minimizes the distance between corresponding n-type and p-type transistors, enabling tight integration with minimal signal path length and reduced latency.
Data Source
AI summary
A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.