Cascaded IIR Filter Memory Layout for Lower RAM and Clock Load
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Solution Overview
Problem
Conventional IIR filters require large RAM space, long read/write times, and high clock frequencies due to the need for storing and reading historical input and output data values, leading to increased cost and power consumption.
Innovation Solution
An IIR filter device with a header data module, intermediate data module, and tail data module that uses address exchange to store and communicate data within registers, reducing the need for RAM storage and lowering clock frequency by optimizing data access methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional serial computation mode is used with N-section cascaded biquad IIR filter, then filtering functionality is achieved, but RAM capacity requirement increases to 5*N words
Solution Approach 1:
The patent divides the filter computation into multiple stages (first stage, second stage, third stage, etc.), where each stage processes specific data elements. The header data module, intermediate data module, and tail data module are segmented to handle different data types separately, reducing the need for unified large RAM storage.
Solution Approach 2:
The patent introduces a time-dimensional approach by using different clock cycles for different computation stages. Data is stored and retrieved in a temporal sequence rather than all simultaneously, allowing the use of smaller storage modules that operate cyclically instead of large static RAM.
2Reliability
If conventional serial computation mode is used with N-section cascaded biquad IIR filter, then filtering functionality is achieved, but computation time requires 10*N clock cycles
Solution Approach 1:
The patent performs preliminary data organization by storing current input data, first historical input data, and second historical input data in the header data module before computation begins. This pre-arrangement eliminates the need for multiple sequential data retrieval operations during computation, reducing total clock cycles required.
Solution Approach 2:
The patent implements continuous data flow through the three modules where the tail data module immediately feeds processed data back to the header data module for the next computation cycle. This eliminates idle time between stages and maintains continuous useful computation action.
3Productivity
If high clock frequency is used to reduce computation time, then filtering speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters by using a lower clock frequency combined with a optimized data storage and retrieval scheme. The modular architecture allows each stage to complete its operation in fewer cycles, achieving the same throughput at lower frequency, thus reducing power consumption.
4Measurement precision
If large RAM space is allocated for storing historical data values, then data access accuracy is improved, but device cost increases
Solution Approach 1:
The patent extracts only the essential historical data elements (current input, first historical input, and second historical input data) needed for IIR filter computation and stores them in dedicated register structures. This selective extraction eliminates the need for large RAM space while maintaining all necessary data for accurate computation.
Data Source
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AI summary
Disclosed in the present application are an IIR filter device and a filtering method thereof. The IIR filter device comprises: a head data module, which stores current input data and two pieces of input historical data; a filtering module, which stores output data of each stage via an intermediate data module first position corresponding to each stage of filtering, switches the addresses of the first position and a second position and, via a calculation module, reads the current input data and the two pieces of input historical data from a designated position, reads two pieces of output historical data from an intermediate data module and stores said data in a tail data module, and after filtering, outputs data and triggers the next stage of filtering; and the tail data module, which is used, when any stage of filtering is complete, for storing the output data of said stage of filtering as input data for the next stage of filtering, the designated position of a first stage of filtering being the head data module, and the designated position of the other stages of filtering being the tail data module. The application reduces data read and write times, avoids interruption of the calculation pipeline, reduces the required data storage by half, and reduces the required clock frequency.