Parallel IIR Predistortion Circuit for Power Amplifier Memory Effects
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Solution Overview
Problem
Power amplifiers in communication systems exhibit nonlinearity, leading to spectral growth and distortions that increase bit error rates and interfere with adjacent channels, making it challenging to meet the performance requirements of new wireless communication applications.
Innovation Solution
A digital predistortion (DPD) system utilizing multiple infinite impulse response (IIR) filters and a combiner circuit to generate predistortion signals that compensate for memory effects of gallium nitride (GaN) transistors, including gate lag, drain lag, and thermal effects, thereby improving the linearity of power amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital predistortion techniques are used to linearize the power amplifier, then linearity is improved, but device complexity increases due to the need for multiple IIR filters and signal paths to compensate for multiple memory effects
Solution Approach 1:
The DPD system is segmented into multiple independent signal paths, each handling a specific memory effect (gate lag, drain lag, thermal effects). Each path contains dedicated IIR filters configured for specific time constants, allowing modular compensation of different memory effects without requiring a single complex system.
Solution Approach 2:
The parallel IIR filter architecture provides a universal framework that can compensate for multiple types of memory effects simultaneously. The system uses the same basic IIR filter structure repeated across different paths, each tuned to different time constants, making the solution universally applicable to various memory effects in GaN power amplifiers.
2Measurement precision
If multiple IIR filters are used to compensate for different memory effects, then compensation accuracy is improved, but processing time increases due to multiple signal paths
Solution Approach 1:
The system performs predistortion processing in advance by pre-configuring multiple IIR filter paths with appropriate time constants before the power amplifier processes the signal. The parallel architecture allows all predistortion calculations to be completed simultaneously in the digital domain before conversion to analog, avoiding sequential processing delays.
Solution Approach 2:
The patent replaces traditional analog compensation methods with digital signal processing using IIR filters. This substitution allows complex multi-path processing to be performed in the digital domain where parallel operations can be executed simultaneously, significantly reducing processing time compared to sequential analog methods.
3Reliability
If parallel signal paths with multiple IIR filters are implemented, then memory effect compensation is improved, but circuit complexity increases
Solution Approach 1:
The compensation circuit is segmented into distinct parallel paths, each dedicated to compensating for specific memory effects (gate lag, drain lag, thermal effects). Each path contains IIR filters with specific time constants matched to the characteristics of particular memory effects, allowing targeted compensation without requiring a monolithic complex circuit.
Solution Approach 2:
The system manages circuit complexity by varying the time constant parameters of IIR filters across different parallel paths rather than using identical circuits. Each path's IIR filters are configured with specific time constants (e.g., 100μs to 10ms range) matched to the time constants of specific memory effects, enabling effective compensation through parameter differentiation rather than structural complexity.
Data Source
AI summary
A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. The DPD system includes a first predistortion circuit configured to provide a first signal path coupled to the input to generate a first predistortion signal. The first predistortion circuit includes a first infinite impulse response (IIR) filter. A second predistortion circuit is configured to provide a second signal path coupled to the input in parallel with the first signal path to generate a second predistortion signal. The second predistortion circuit includes a second IIR filter. A combiner circuit is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.