IJTAG Hierarchical Access Time Reduction via SIB Registers
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Solution Overview
Problem
The hierarchical design of electronic devices using JTAG or IJTAG standards results in increased access time to test data registers due to the need for multiple iterations through hierarchical levels, leading to a significant number of clock cycles required to access or program these registers.
Innovation Solution
The introduction of de-asserted segment insertion bit (D-SIB) registers and asserted segment insertion bit (A-SIB) registers, where D-SIB prevents access to its associated TDR upon a reset signal, while A-SIB provides access to other D-SIB and A-SIB registers within the same or child hierarchical levels, allowing access to desired TDRs within the same iteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hierarchical design is used to organize electronic components, then device complexity is reduced and modularity is improved, but access time to test data registers increases due to multiple iterations through hierarchical levels
Solution Approach 1:
The patent segments the hierarchical access control into multiple types of segment insertion bit (SIB) registers: default SIB registers, asserted SIB registers, and de-asserted SIB registers. Each type controls access to specific hierarchical levels independently, allowing parallel access paths rather than sequential iteration through all levels. This segmentation resolves the contradiction by maintaining hierarchical organization while enabling direct access to target registers without traversing intermediate levels.
Solution Approach 2:
The patent introduces dynamic control mechanisms where SIB registers can be asserted or de-asserted based on operational requirements. The asserted SIB registers enable access to child hierarchical levels, while de-asserted SIB registers prevent access to specific levels. This dynamic configuration allows the system to adapt access paths in real-time, maintaining the benefits of hierarchical design while minimizing access time by activating only the necessary access paths for the current operation.
2Reliability
If multiple iterations are performed to access TDR at deeper hierarchical levels, then proper access control is maintained, but the number of clock cycles required increases significantly
Solution Approach 1:
The patent implements preliminary action by pre-configuring the SIB register states before access operations. The default SIB registers are pre-set to control normal hierarchical access, while asserted and de-asserted SIB registers are pre-configured to enable or disable specific access paths. This preliminary configuration allows the system to execute access operations directly without requiring multiple iterative cycles, thereby maintaining reliable access control while significantly improving programming speed for TDR at deeper hierarchical levels.
Solution Approach 2:
The patent introduces SIB registers as intermediary control elements between the test access port and the hierarchical network. These intermediary registers act as gatekeepers that can selectively enable or disable access to specific hierarchical levels without requiring sequential iteration. The asserted SIB registers serve as mediators to grant access to child levels, while de-asserted SIB registers mediate to block access to specific levels, thus maintaining access control reliability while enabling direct, high-speed access to target registers.
Data Source
AI summary
A system includes a test access port (TAP) configured to provide internal joint test action group (IJTAG) access to one or more test data registry (TDR). The system further includes a plurality of hierarchical electronic components, wherein each hierarchical electronic component includes a de-asserted segment inserted bit (D-SIB) register, an asserted segment inserted bit (A-SIB) register, and a TDR associated with the D-SIB register. Each D-SIB register is configured to prevent access to its associated TDR when a reset signal is asserted and each A-SIB register is configured to provide access to its subsequent A-SIB register or D-SIB register coupled thereto when the reset signal is asserted.