Compacting IJTAG Test Patterns for IP Blocks
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Solution Overview
Problem
Existing electronic design automation (EDA) systems require extensive test cycles for verifying complex circuit designs, leading to inefficient use of test machine resources and prolonged testing times, especially when dealing with multiple instances of integrated functional blocks (IP blocks) in ASICs and SOCs.
Innovation Solution
The implementation of a method to compact test patterns by merging test operations across multiple instances of IP blocks, using IEEE 1687 standards for test access port and boundary scan operations, and applying these compacted patterns in parallel to reduce the number of test cycles required, thereby improving test machine efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional separate test operations are applied to multiple instances of IP blocks, then comprehensive testing coverage is achieved, but test cycles and resource usage increase significantly
Solution Approach 1:
The patent merges test operations across multiple instances of IP blocks by identifying equivalent test patterns and consolidating them into unified test sequences. Test machines apply compacted test patterns in parallel to multiple IP block instances, reducing redundant testing while maintaining comprehensive coverage. This merging approach directly reduces test cycles and resource usage without compromising testing reliability.
2Manufacturing precision
If comprehensive test patterns are applied to verify complex circuit designs, then manufacturing quality is ensured, but test machine efficiency decreases
Solution Approach 1:
The system consolidates comprehensive test patterns into compacted representations that maintain full verification capability while reducing test machine workload. By merging equivalent test operations across IP block instances and applying them in parallel, the system ensures manufacturing quality through thorough verification while improving test machine efficiency and throughput.
Solution Approach 2:
The patent creates universal test patterns that can be applied across multiple IP block instances simultaneously. These compacted test patterns serve multiple functions: they verify fabrication quality, test functional correctness, and validate interconnect integrity across different IP block instances using a unified test approach, thereby improving productivity without sacrificing verification comprehensiveness.
3Measurement precision
If separate test operations are performed for each IP block instance, then detailed verification is achieved, but resource usage and testing time increase
Solution Approach 1:
The system merges detailed verification operations by identifying equivalent test patterns across IP block instances and consolidating them into unified test sequences. Test machines apply these compacted patterns in parallel, maintaining detailed measurement precision for each instance while significantly reducing overall resource usage and testing time through efficient resource utilization.
Data Source
AI summary
Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.