Interlevel Dielectric Composition Tuning for Strained Transistors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in semiconductor integrated circuits is to improve transistor performance by enhancing charge carrier mobility and reducing undesired oxygen concentrations while managing complex processing and manufacturing complexities due to scaling down.

Innovation Solution

The implementation of an interlevel dielectric layer with varying compositions achieved through patterning and ion implantation processes, which imparts beneficial strain to the source/drain regions of transistors, reducing oxygen concentrations and capacitance equivalent thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation is performed on the interlevel dielectric layer, then charge carrier mobility is enhanced and transistor performance is improved, but the processing complexity increases

Engineering Contradiction:
Improvetransistor performanceVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interlevel dielectric layer is divided into multiple portions (first portion, second portion, third portion) with different material compositions. This segmentation allows selective ion implantation in specific regions (second portion) while maintaining original properties in other regions, enabling targeted transistor performance enhancement without uniformly complicating the entire processing flow.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the interlevel dielectric layer are assigned different material compositions tailored to specific functional requirements. The second portion receives ion implantation to create beneficial strain in underlying source/drain regions, while first and third portions maintain original compositions for their respective functions, achieving local optimization without global processing complexity.

Inventive Principle:
Principle #3Local quality

2Reliability

If the interlevel dielectric layer composition is varied to reduce oxygen concentrations, then charge carrier mobility improves, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvecharge carrier mobilityVSAvoidcomposition control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The interlevel dielectric layer is formed with predetermined material compositions in different portions before ion implantation. The second portion is pre-configured with specific material properties that, when combined with subsequent ion implantation, will achieve the desired oxygen concentration reduction and strain effects, allowing precise control through preparatory material selection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The material composition parameters of the interlevel dielectric layer are systematically varied across different portions. By changing composition parameters (such as dielectric material type and doping levels) in the second portion while maintaining standard compositions in other portions, the invention achieves targeted oxygen concentration control and strain optimization with manageable precision requirements.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances charge carrier mobility, improves transistor performance, and reduces undesired oxygen concentrations, leading to improved current performance and reduced capacitance in both N-type and P-type transistors.

Implementation Method 1

an ion implantation process is then performed to change the composition of the exposed second portion of the interlevel dielectric layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS20250338558A1Integrated circuit with ion implantation in ild
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250338558A1 patent drawing
  • US20250338558A1 patent drawing
  • US20250338558A1 patent drawing

AI summary

An integrated circuit includes an interlevel dielectric layer having a first portion directly above a source/drain region of a transistor and a second portion directly above the source/drain region and laterally abutting the first portion. The first and second portions have different material compositions such that that the interlevel dielectric region imparts a beneficial strain to the transistor.