ILD Layer Densification for Void-Free BEOL Interconnects
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Solution Overview
Problem
Conventional methods for fabricating back-end-of-the-line interconnect structures in integrated circuits often result in voids due to undercuts and bowing during the etching process, leading to incomplete metal filling and increased resistance in the interconnect structure.
Innovation Solution
Densifying the upper-surface portion of the ILD layer through a plasma treatment process to form a densified surface layer with a similar lateral etch rate to the ILD layer, eliminating the need for a dense cap layer and preventing voids by ensuring complete metal filling of via-holes and metal line trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dense cap layer is deposited over the porous ILD layer to protect it, then the ILD layer is protected, but undercuts and bowing occur during etching due to the significant difference in lateral etch rates between the dense cap layer and the porous ILD layer
Solution Approach 1:
The patent applies a porous ILD layer with controlled porosity (e.g., 10-50%) that provides both protection and etch rate consistency. The local quality of the dielectric layer is optimized to balance protective function with etching uniformity, eliminating the need for a separate dense cap layer while preventing undercuts and bowing during via-hole etching.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dielectric layer by controlling its porosity within a specific range (10-50%). This parameter adjustment allows the ILD layer to exhibit both protective characteristics and consistent lateral etch rate, resolving the contradiction between protection and etching uniformity without requiring a dense cap layer.
2Quantity of substance
If a porous dielectric material is used as ILD layer to achieve low-k properties, then the dielectric constant is reduced, but the lateral etch rate becomes significantly higher than that of dense cap layers
Solution Approach 1:
The patent optimizes the porosity parameter of the dielectric layer to fall within the range of 10-50%, which maintains the low-k property (reduced dielectric constant) while simultaneously achieving etch rate consistency. This parameter control allows the porous ILD layer to etch at a uniform rate without requiring a dense cap layer, preventing undercuts and bowing.
Solution Approach 2:
The patent creates a locally optimized dielectric layer with controlled porosity distribution that maintains low-k properties in the bulk while achieving surface characteristics that provide etch rate consistency. The local quality of the porous structure is tuned to balance dielectric performance with etching uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents void formation in the interconnect structure, enhancing the reliability and performance of the BEOL interconnect by maintaining consistent etch rates and ensuring complete metal filling without undercuts or bowing.
Implementation Method 1
An upper-surface portion of the ILD layer is exposed to a plasma treatment process to densify the upper-surface portion and form a densified surface layer of dielectric material
Data Source
AI summary
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer.