ILD Replacement with Source/Drain Capping for Low-k Dielectrics
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in reducing parasitic capacitance between active FET devices due to damage and contamination of low-k dielectric materials used in interlayer dielectric layers during processes like reactive ion etching and thermal annealing, leading to increased effective dielectric constant and reduced device performance.
Innovation Solution
Implementing an ILD replacement process that forms silicide or dielectric capping layers to protect source/drain contacts during the ILD replacement, allowing for the selective removal of sacrificial interlayer dielectric layers and subsequent deposition of low-k interlayer dielectric layers, thereby maintaining low dielectric constant and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If low-k dielectric material is used to form the initial ILD layer to reduce parasitic capacitance, then parasitic capacitance is reduced, but the low-k dielectric material becomes damaged and contaminated during fabrication processes, leading to increased effective dielectric constant
Solution Approach 1:
A sacrificial ILD layer is formed initially to protect the low-k dielectric material during subsequent fabrication processes. The sacrificial layer serves as a buffer that can be removed later, preventing direct exposure and damage to the low-k material during etching and other aggressive processes.
Solution Approach 2:
The sacrificial ILD layer acts as an intermediary between the fabrication processes and the low-k dielectric material. It absorbs the harmful effects of etching and processing, thereby protecting the low-k material from contamination and damage while allowing the necessary fabrication steps to proceed.
2Object-generated harmful factors
If the sacrificial interlayer dielectric layer is removed to replace with low-k ILD layer, then parasitic capacitance is reduced, but source/drain contacts are exposed to etch damage
Solution Approach 1:
Metal-semiconductor alloy capping layers are formed on the source/drain contacts before the etch process that removes the sacrificial ILD layer. These capping layers serve as protective barriers that prevent etch damage to the contacts during the sacrificial layer removal process.
Solution Approach 2:
The metal-semiconductor alloy capping layers act as intermediary protective layers between the etch process and the source/drain contacts. They are selectively etched away after serving their protective function, allowing the contacts to remain undamaged throughout the process.
3Adaptability or versatility
If multiple fabrication processes are performed to form source/drain contacts and metal gates, then device functionality is achieved, but the low-k dielectric material becomes damaged and contaminated
Solution Approach 1:
The sacrificial ILD layer is formed in advance before the source/drain contact and metal gate fabrication processes. This preliminary structure provides ongoing protection during all subsequent processing steps, allowing complex device fabrication while maintaining low-k material integrity.
Solution Approach 2:
The sacrificial ILD layer serves as a continuous intermediary protective structure throughout the entire fabrication sequence, including source/drain contact formation and metal gate processing. It can be selectively removed when no longer needed, having protected the low-k material during all critical processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and protects source/drain contacts from etch damage, enhancing device performance and power efficiency by maintaining a low-k dielectric constant, thus addressing the limitations of existing techniques.
Implementation Method 1
performing an etch process to remove the sacrificial interlayer dielectric layer, wherein the etch process is selective to the metal-semiconductor alloy capping layers such that the metal-semiconductor alloy capping layers protect the metallic source/drain contacts from etch damage during the etch process
Implementation Method 2
performing a thermal anneal process to induce a reaction between the semiconductor layer and the metallic source-drain contacts to form metal-semiconductor alloy capping layers in upper surface regions of the metallic source/drain contacts
Data Source
AI summary
Techniques are provided for fabricating a semiconductor integrated circuit device which implement an interlayer dielectric (ILD) layer replacement process to replace an initial sacrificial ILD layer with a low-k ILD layer, while forming silicide or dielectric capping layers to protect source/drain contacts of field-effect transistor devices from etch damage during the ILD replacement process. For example, source/drain contact openings (e.g., trenches) are formed in a sacrificial ILD layer and metallic source/drain contacts are formed in the source/drain contact openings. Protective capping layers (e.g., metal-semiconductor alloy capping layers or dielectric capping layers) are formed on upper surfaces of the metallic source/drain contacts. The sacrificial ILD layer is removed using an etch process to etch down the sacrificial ILD layer selective to the protective capping layers, and a low-k ILD layer is formed in place of the removed sacrificial ILD layer.