Interlayer Dielectric Stack Stress Balancing for Wafer Bow Reduction

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Solution Overview

Problem

Monolithic integrated circuit (IC) fabrication is limited by wafer bow, which can cause manufacturing issues and tool incompatibilities due to excessive strain and shape deformation, leading to stranded wafers and reduced manufacturing efficiency.

Innovation Solution

The implementation of a stress modulation layer and a capping layer within the interlayer dielectric structure to mitigate wafer bow by applying opposing intrinsic stress, using materials like silicon dioxide and silicon nitride to correct distortions and facilitate subsequent metallization processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple IC dies are fabricated on a silicon wafer with layers having significant intrinsic stress, then the wafer can be bonded and stacked to create multi-chip packages or wafer-level stacked devices, but the intrinsic stress causes the wafer to bow, resulting in manufacturing issues and tool incompatibilities

Engineering Contradiction:

Improvemulti-chip package integrationVSAvoidwafer flatness

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

A stress modulation layer is formed on the wafer surface before subsequent processing steps to preemptively counteract the intrinsic stress that would cause bowing. This layer applies an opposing stress that prevents the wafer from bowing during manufacturing, allowing the wafer to remain flat and compatible with manufacturing tools while enabling multi-chip package integration.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The intrinsic stress state of the wafer is modified by introducing a stress modulation layer with controlled stress properties. By adjusting the thickness, material composition, and stress characteristics of this layer, the overall stress balance of the wafer structure is changed, transforming the bowing problem into a controllable parameter that can be optimized for both flatness and integration capability.

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If a wafer with excessive bow is processed in manufacturing tools, then the tool can handle the wafer, but the wafer may become stranded within the tool, requiring time-consuming intervention and reducing manufacturing efficiency

Engineering Contradiction:

Improvetool compatibilityVSAvoidmanufacturing efficiency

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The stress modulation layer is applied in advance to prevent bowing before the wafer enters the manufacturing tool. This preliminary counteraction ensures the wafer maintains sufficient flatness for tool compatibility, eliminating the risk of the wafer becoming stranded and avoiding time-consuming interventions, thereby maintaining high manufacturing efficiency.

Inventive Principle:

Principle #9Preliminary anti-action

3Adaptability or versatility

If layers with significant intrinsic stress are used in the wafer structure, then the wafer can be singulated into multiple stacked chip packages, but the strain within the layer causes the shape to change, resulting in a bowed shape

Engineering Contradiction:

Improvewafer singulation capabilityVSAvoidlayer flatness

Core Design Contradiction:

Adaptability or versatilityVSShape

Solution Approach 1:

The stress modulation layer is applied specifically to the regions of the wafer where intrinsic stress causes bowing. By locally counteracting the stress in affected areas, the layer maintains the flatness of critical regions while allowing the wafer to be successfully singulated into multiple stacked chip packages.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively reduces wafer bow by up to 200 micrometers, enabling compatibility with existing manufacturing tools and processes, and facilitating the integration of multiple IC dies into a single package.

Implementation Method 1

a first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer

Methodology Applied

Scientific EffectIntrinsic stress:

Data Source

PatentUS12431441B2Interlayer dielectric stack optimization for wafer bow reduction

Publication Date: 2025.09.30 INTEL CORP

AI summary

An integrated circuit (IC) die comprises a first metallization layer comprising first interconnect structures which each extend through the first metallization layer, a second metallization layer comprising second interconnect structures which each extend through the second metallization layer, an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer. The ILD stack comprises a stress modulation layer on the first metallization layer and a capping layer on the stress modulation layer. A first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer.