ILD0 Stack Void Elimination via Planarized Gettering Layer
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Solution Overview
Problem
Existing semiconductor fabrication processes result in voids in the first inter-layer dielectric (ILD0) layer, which traps mobile ions and reduces device yield, leading to performance impairments and stringer shorts, especially in non-volatile memory devices.
Innovation Solution
A method involving the deposition of an etch stop layer followed by a gap fill layer to cover and fill regions between semiconductor devices, with subsequent planarization and formation of a gettering layer to ensure uniform thickness and protection against mobile ions, using materials like SATEOS, HDP oxide, and BPTEOS, and a capping layer for structural support and impurity protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a BPTEOS layer is deposited non-conformally to fill gaps between device components, then the gap filling is achieved, but void regions form in the layer
Solution Approach 1:
A planarization layer is formed over the device components before depositing the BPTEOS gettering layer. This preliminary planarization creates a flat surface that enables conformal deposition of the gettering layer, preventing void formation while maintaining effective gap filling and mobile ion protection.
2Manufacturing precision
If the BPTEOS layer is polished during planarization to expose underlying devices, then planarization is achieved, but the protective gettering function is removed or reduced
Solution Approach 1:
The interlayer dielectric structure is segmented into multiple functional layers: a planarization layer for surface flattening, a BPTEOS gettering layer for mobile ion protection, and additional dielectric layers. This segmentation allows the planarization layer to be polished away while preserving the underlying gettering layer's protective function.
Solution Approach 2:
The planarization layer is formed in advance over the device components, serving as a sacrificial layer that can be selectively removed by CMP polishing. This preliminary layer protects the underlying BPTEOS gettering layer during planarization, ensuring the gettering function is maintained while achieving the required surface planarity.
3Object-affected harmful factors
If mobile ions are trapped in void regions of the ILD0 layer, then ion trapping occurs, but device yield and performance are reduced
Solution Approach 1:
The harmful void regions are eliminated by introducing a planarization layer that enables conformal deposition of the BPTEOS gettering layer. This extraction of voids prevents mobile ion trapping sites, thereby maintaining high device yield and performance while preserving the ion protection function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces voids, enhances gettering protection, and increases manufacturing yield by forming a void-free ILD0 stack with uniform thickness, effectively preventing mobile ion trapping and stringer shorts.
Implementation Method 1
a gap fill layer is formed over the plurality of device components to fill regions between the plurality of device components
Implementation Method 2
The gap fill layer is then planarized down to a substantially planar surface
Implementation Method 3
a dielectric gettering layer is formed over the substantially planar surface
Implementation Method 4
the etch stop layer and gap fill layer are selectively etched to expose contact regions in the plurality of device components
Data Source
AI summary
A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.