Injection-Locked Oscillator Calibration Using TDC Codes for Low Jitter
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Solution Overview
Problem
Electronic circuits face challenges in maintaining stable operation across varying supply voltages and temperatures due to changes in electrical characteristics, which affect their behavior and jitter performance.
Innovation Solution
The use of an injection-locked oscillator (ILO) circuitry that adjusts its natural oscillation frequency to match the reference clock frequency by modifying delay elements, minimizing jitter and enhancing tolerance to voltage and temperature drift through a process involving injection signals, sampling, and control circuitry to determine optimal settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ILO operates over a range of supply voltages and temperatures, then the circuit must be adaptable to different operating conditions, but the electrical characteristics of circuit elements change, causing jitter performance to deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the ILO's output is sampled and compared to a reference clock signal. The phase difference detected by the sampling circuitry is fed back to adjust the delay elements, automatically compensating for voltage and temperature drift to maintain stable operation across varying operating conditions
Solution Approach 2:
The patent dynamically adjusts the delay element parameters in response to detected phase errors. By changing the delay characteristics based on feedback from the sampling circuitry, the system adapts to varying operating conditions while maintaining consistent jitter performance
2Reliability
If the natural oscillation frequency of the ILO is adjusted to match the reference clock frequency, then output jitter is minimized, but this requires dynamic modification of delay elements which increases control circuitry complexity
Solution Approach 1:
The sampling circuitry serves multiple functions: it samples the ILO output, compares it with the reference clock, detects phase differences, and generates feedback signals. This multi-functionality reduces the need for separate dedicated circuits, thereby minimizing the increase in overall system complexity while achieving jitter minimization
Solution Approach 2:
The system uses its own output signal to generate the feedback necessary for adjustment. The ILO's output is sampled and used to detect phase differences, which then drive the delay element adjustments, creating a self-regulating mechanism that minimizes jitter without requiring external complex control systems
3Reliability
If delay elements are modified to align the ILO's natural frequency with the reference clock frequency, then tolerance to voltage and temperature drift is maximized, but this requires a calibration process that consumes time
Solution Approach 1:
The patent performs frequency calibration by measuring the phase difference between the ILO output and reference clock, then pre-adjusting the delay elements to compensate for expected drift. This preliminary adjustment establishes optimal operating parameters before normal operation begins, maximizing tolerance to voltage and temperature variations
Solution Approach 2:
The continuous feedback mechanism allows the system to make real-time adjustments to delay elements based on detected phase errors. This ongoing calibration process maintains optimal tolerance to drift conditions without requiring lengthy periodic recalibration, reducing time loss while maximizing reliability
Data Source
Figure 1~2A
Figure 2B
Figure 2C~2D
AI summary
Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.