3D IC Inter-Layer Vias for High-Density Memory Read Accuracy
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Solution Overview
Problem
Current 3D packaging technologies face challenges in achieving high integration density and reliable read operations due to weak bit scenarios in memory cells, where the driving current is insufficient, leading to inaccurate read operations and reduced storage capacity.
Innovation Solution
A 3D Integrated Circuit (IC) design with stacked layers of NMOS and PMOS transistors, utilizing Through Substrate Vias (TSVs), Inter-Layer Vias (ILVs), and Inter-Tier Vias to connect transistors, and incorporating redundant ROM devices that can activate inactive portions to enhance driving current and improve read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D packaging technology is used to increase integration density, then storage capacity is improved, but read operation accuracy deteriorates due to weak bit scenarios
Solution Approach 1:
The patent transitions from planar 2D packaging to three-dimensional stacked architecture, where memory cells are arranged in multiple tiers along the vertical dimension. Through-substrate vias (TSVs) and inter-layer vias (ILVs) enable electrical connections between tiers, achieving high integration density by utilizing the third dimension for stacking multiple active layers.
Solution Approach 2:
The memory structure is divided into multiple functional tiers: first and second memory cell tiers with alternating NMOS and PMOS transistors, separate word line tiers, bit line tiers, and redundancy tiers. This segmentation allows independent optimization of each tier and enables the weak bit correction mechanism to operate on specific segments without affecting the entire array.
2Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated, but driving current becomes insufficient leading to weak bit scenarios
Solution Approach 1:
The patent merges multiple transistor types (NMOS and PMOS) into complementary pairs within the same memory cell tier. This complementary configuration allows the cell to leverage both n-type and p-type carrier mobility, enhancing the overall driving current capability despite reduced individual transistor dimensions. The merged structure also enables differential signaling for improved read margin.
Solution Approach 2:
The memory cell design uses universal complementary transistor pairs that can serve multiple functions: storage, driving current generation, and weak bit correction. The same structural units are reused across different tiers with alternating configurations, providing scalability and maintaining performance across the three-dimensional structure.
3Reliability
If redundant ROM devices are added to correct weak bits, then read operation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements redundancy by creating duplicate copies of memory cell tiers and associated circuitry. First and second memory cell tiers are mirrored with complementary transistor configurations, and redundancy word lines are copied from primary word lines. These copies serve as backup pathways to correct errors in the original structure without requiring entirely separate correction circuits.
Solution Approach 2:
The redundant memory tiers and correction circuitry are pre-configured during fabrication alongside the primary memory structure. The complementary transistor pairs and via connections are established in advance, enabling immediate weak bit correction functionality without requiring additional dynamic reconfiguration or complex control logic during operation.
Data Source
AI summary
A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.