Image Processing Buffer Memory Data Rate Control
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Solution Overview
Problem
High-speed data processing in image capturing devices like digital cameras is hindered by increased memory bus bandwidth, leading to reduced still image continuous shooting frame speed and moving image frame rate, with existing solutions either degrading image quality or increasing cost and power consumption.
Innovation Solution
An image processing device with a buffer memory and data rate adjusting circuit that temporarily stores and outputs image data at varying rates, averaging peak data rates during invalid periods to prevent memory bus bandwidth overload without reducing image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data rate is increased to process more image data per unit time, then the volume of data processed per unit time is improved, but the memory bus bandwidth is taken up and the data processing rate of image processing is reduced
Solution Approach 1:
The patent applies preliminary action by performing data rate adjustment before data is written into the memory. The data rate adjusting circuit pre-processes the image data by controlling the timing and rate of data output from the buffer memory, ensuring that data is fed to the memory at an optimized rate that prevents bandwidth overload while maintaining high processing throughput.
Solution Approach 2:
The patent uses an intermediary approach by introducing a data rate adjusting circuit as a mediator between the buffer memory and the recording memory. This intermediary circuit controls the data flow rate, adjusting it to match the memory bus bandwidth capacity, thereby preventing bandwidth saturation while maintaining high productivity in data processing.
2Productivity
If the memory bus bandwidth is increased by increasing processing frequencies or data width, then the data processing capability is improved, but the cost and power consumption are increased
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the data rate parameter rather than increasing the memory bus bandwidth hardware specifications. The data rate adjusting circuit modifies the timing and frequency of data transfers to match the available bandwidth, achieving high productivity without the need for higher frequency or wider data bus configurations that would increase power consumption and cost.
3Speed
If captured image data is compressed or reduced to achieve a data rate that can be processed, then the data processing speed is improved, but the amount of information is reduced and the quality of recorded image is degraded
Solution Approach 1:
The patent applies dynamics by implementing a dynamic data rate adjustment mechanism that adapts to the actual data flow characteristics. The data rate adjusting circuit continuously monitors and adjusts the output rate from the buffer memory based on the input data rate and memory write capacity, maintaining optimal processing speed without compressing or reducing the image data, thereby preserving full image quality.
Data Source
AI summary
An image processing device includes a buffer memory configured to temporarily store image data, setting circuit for setting a first data rate at which the image data is transferred to a recording memory, and adjusting circuit for adjusting a data rate by causing a portion of image data read from the image sensor to be temporarily stored in the buffer memory when a second data rate exceeds the first data rate, and causing the temporarily stored portion of the image data to be output from the buffer memory when the second data rate is lower than the first data rate, the portion of the image data corresponding to an amount by which the second data rate exceeds the first data rate.