Image Processing Cache Bank Interleave Method
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Solution Overview
Problem
Image processing systems face performance degradation due to varying access patterns and increased transfer lengths when using shared DRAM storage, particularly in tasks like deforming and combining images of different shapes, which are not effectively addressed by existing cache management techniques.
Innovation Solution
An image processing apparatus with a cache device that employs a bank interleave method to divide images into pixel fragments and store them in local memories, allowing for efficient handling of changing access patterns and transfer lengths, thereby maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shared DRAM storage device is used to reduce cost, then manufacturing cost is reduced, but access latency increases and processing performance degrades
Solution Approach 1:
The patent divides the DRAM storage device into multiple banks and implements a bank interleave method where different banks can be accessed simultaneously. This segmentation allows parallel access operations, reducing the effective access latency while maintaining the cost benefits of shared DRAM storage.
Solution Approach 2:
The patent implements a cache device that performs preliminary action by prefetching image data into the cache memory before it is actually needed for processing. This anticipatory data loading hides the DRAM access latency, as the cache can supply data to the processor without waiting for DRAM access.
2Productivity
If cache devices are provided to suppress performance degradation, then processing performance is improved, but circuit scale increases
Solution Approach 1:
The patent implements a cache memory with specific organizational structures (direct-mapped, fully-associative, or set-associative) that optimize for the local access patterns of image processing workloads. The cache is designed with specific parameters (size, associativity, block size) tailored to the particular image processing application, providing high performance without excessive circuit scale.
Solution Approach 2:
The patent implements dynamic cache replacement policies (LRU, FIFO, random) that adapt to different access patterns. The cache controller dynamically selects replacement victims based on current workload characteristics, optimizing performance for varying image processing tasks while maintaining a fixed physical cache size.
3Productivity
If images are read out with increased transfer length to maintain DRAM performance, then DRAM efficiency is improved, but access pattern complexity increases
Solution Approach 1:
The patent implements continuous data transfer from DRAM to cache using burst transfer modes that maintain high throughput. The bank interleave method ensures continuous access by switching between banks, eliminating idle cycles and maintaining DRAM efficiency while the cache handles the complexity of data reorganization.
Solution Approach 2:
The cache memory acts as an intermediary between the DRAM and the image processing circuit. It receives data in large bursts from DRAM using simple linear addressing, then reformats and supplies data to the processor in smaller, processing-friendly units. This mediator role simplifies the access pattern for both DRAM and processor.
Data Source
AI summary
An image processing apparatus that performs filtering by reading out an image from an external storage unit, the image being divided into a plurality of banks by a first interleave method according to a transfer length when the image is read out from the external storage unit is provided. The apparatus including: a plurality of local memories; and a control unit configured to divide, into a plurality of pixel fragments, a pixel of a bank which includes at least one of a plurality of pixels needed for the filtering by a second interleave method according to the transfer length and store each of the pixel fragments obtained as a result of division in one of the plurality of local memories in accordance with the transfer length.