Image Capture Accelerator Bypasses ISP Bandwidth Limits
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Solution Overview
Problem
Image Signal Processing (ISP) ASICs face bandwidth limitations and high power consumption, hindering the ability to process image sensor frames at high resolutions and frame rates, which restricts the capabilities of digital camera systems.
Innovation Solution
An image capture accelerator (ICA) is introduced to bypass traditional ISP processing, incorporating a pre-processing engine and compression engine to accelerate image data processing, allowing for higher bandwidth and reduced power usage by operating in accelerated modes for high-resolution and high-frame-rate image capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional ISP processing is used, then image processing capability is maintained, but bandwidth limitations and high power consumption occur
Solution Approach 1:
The system divides image processing into two segments: a first image processing pipeline for generating lower-resolution preview images, and a second image processing pipeline for generating higher-resolution final images. This segmentation allows the lower-resolution pipeline to handle real-time preview generation with reduced power consumption, while the higher-resolution pipeline processes images at lower frame rates, overall reducing the power burden on the ISP.
Solution Approach 2:
The patent applies partial action by processing only a subset of captured images at full resolution. Specifically, every Nth frame is processed at full resolution while other frames are processed at lower resolution for preview purposes. This partial processing approach reduces the total computational load and power consumption while still providing high-quality images at appropriate intervals.
2Productivity
If image sensor captures at higher resolutions and frame rates, then image quality and capture speed improve, but ISP bandwidth limitations prevent effective processing
Solution Approach 1:
The system dynamically adjusts processing resolution based on frame requirements. A determination module decides whether each frame should be processed at full resolution or lower resolution, allowing the system to adaptively manage ISP bandwidth. This dynamic adjustment enables the system to capture at high frame rates while processing only necessary frames at full resolution, effectively bypassing ISP bandwidth limitations.
Solution Approach 2:
The patent introduces an intermediary processing path that bypasses the traditional ISP for certain frames. A separate image processing circuit processes selected frames independently from the main ISP pipeline, acting as an intermediary that reduces the burden on the ISP while still delivering high-resolution output. This intermediary path enables the system to handle higher capture rates without overwhelming the ISP.
3Measurement precision
If full-resolution images are processed at high frame rates, then image quality is maintained, but power consumption exceeds battery capacity
Solution Approach 1:
The system applies local quality by providing different resolution qualities for different purposes. Preview images are generated at lower resolution for real-time display, while final captured images are processed at full resolution. This local differentiation of quality levels allows the system to maintain battery life through lower-resolution preview processing while still delivering high-quality final images when needed.
Solution Approach 2:
The patent implements periodic full-resolution processing where every Nth frame is captured and processed at full resolution, while other frames are processed at lower resolution. This periodic approach to high-quality processing reduces average power consumption while still providing full-resolution images at regular intervals, balancing image quality requirements with battery life constraints.
Data Source
AI summary
An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.