Image Capturing Device Buffering Vertical Scanning Signals
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Solution Overview
Problem
Conventional CMOS-type solid-state image capturing devices face challenges in efficiently supplying control signals to pixels, leading to deviations in signal timing and increased wiring resistance, capacitance, and load, which affect the sharpness of the control signal waveform, especially for pixels distant from the vertical scanning circuit.
Innovation Solution
The design incorporates multiple substrates with overlapping configurations, featuring vertical scanning circuits and buffers arranged to overlap the pixel unit, with buffers connected to signal lines to transmit control signals, reducing wiring resistance and capacitance, and ensuring sharp waveform delivery to all pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control signals are supplied from a vertical scanning circuit to pixels in a conventional CMOS type solid-state image capturing device, then the device can read signal charge from photoelectric conversion elements, but wiring resistance and capacitance increase for pixels distant from the scanning circuit, causing signal timing deviations and reduced waveform sharpness
Solution Approach 1:
The patent divides the pixel array into multiple regions, each served by a separate vertical scanning circuit. This segmentation reduces the wiring length from the scanning circuit to individual pixels, thereby reducing wiring resistance and capacitance, and minimizing signal timing deviations while maintaining reliable control signal delivery across the entire pixel array
Solution Approach 2:
The patent introduces buffer circuits as intermediary elements between the vertical scanning circuit and the pixels. These buffers act as mediators that receive control signals from the scanning circuit and redistribute them to pixels, effectively reducing the impact of wiring resistance and capacitance on signal timing accuracy for distant pixels
2Productivity
If the number of pixels is small, then control signals can be substantially simultaneously supplied to multiple pixels of the same row, but wiring resistance and capacitance increase for pixels far from the scanning circuit, affecting waveform sharpness
Solution Approach 1:
The patent segments the pixel array into multiple regions served by different vertical scanning circuits, reducing wiring length and resistance/capacitance for each segment. This allows simultaneous signal supply to multiple pixels while maintaining waveform sharpness by limiting the maximum wiring length in each segment
Solution Approach 2:
Buffer circuits are introduced as intermediaries between the scanning circuit and pixels to reduce the harmful effects of wiring resistance and capacitance. These buffers ensure that control signals maintain their sharpness when supplied to pixels at various distances, enabling high-speed simultaneous reading without degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes signal timing deviations and enhances the sharpness of control signals across all pixels, improving the image capturing device's performance by reducing wiring resistance and capacitance, even for pixels far from the scanning circuit.
Implementation Method 1
The CMOS type solid-state image capturing device converts exposure light to signal charge through a photoelectric conversion element in a pixel
Data Source
AI summary
An image capturing device includes: a first substrate; a second substrate arranged so that the second substrate overlaps the first substrate; a pixel unit having a plurality of pixels arranged in a matrix shape on the first substrate; a first vertical scanning circuit arranged on one of the first substrate and the second substrate and configured to output a control signal supplied to every row or every two or more rows of the plurality of pixels; and a plurality of first buffers arranged on the second substrate so that the plurality of first buffers overlap the pixel unit, provided in correspondence with one row or a plurality of rows of the plurality of pixels, and connected to respective signal lines through which the control signal output from the first vertical scanning circuit is transmitted.