Image Capturing Apparatus Synchronization Code Skew Correction
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Solution Overview
Problem
Existing image capturing systems face synchronization challenges due to the use of multiple PLL circuits and P/S converters, leading to asynchronous serial clocks and data synchronization issues, particularly when two or more P/S converters share a single PLL circuit or when multiple PLL circuits are used.
Innovation Solution
An image capturing apparatus is designed with a sensor unit that outputs pixel signals with synchronization codes on multiple transmission paths, and an image processing unit that includes correction units to synchronize the data by detecting the synchronization code and correcting intra-link and inter-link skews, ensuring timely data alignment across paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple PLL circuits are used to generate serial clocks for multiple P/S converters, then high-speed data transfer is achieved, but synchronization between data paths is lost
Solution Approach 1:
The patent divides the data transfer system into multiple independent paths, each with its own P/S converter and PLL circuit. This segmentation allows each path to operate independently at high speed while the synchronization code mechanism ensures overall coordination, resolving the contradiction between speed and synchronization.
Solution Approach 2:
The synchronization code acts as an intermediary element inserted into the data stream. It mediates between the independent PLL circuits by providing a reference point that allows the receiving end to detect and correct timing differences, thereby maintaining synchronization across multiple high-speed paths.
2Device complexity
If two or more P/S converters share one PLL circuit, then device complexity is reduced, but synchronous relationship is canceled due to reset timing differences
Solution Approach 1:
The patent extracts the synchronization function from the PLL circuit itself by inserting a dedicated synchronization code into the data stream. This separates the clock generation function (handled by shared PLL) from the synchronization function (handled by synchronization code), allowing multiple P/S converters to share one PLL without losing synchronous relationship.
Solution Approach 2:
The synchronization code is inserted in advance into the data stream before transmission. This preliminary action provides a predetermined reference point that enables the receiving end to anticipate and correct timing differences caused by reset timing variations, ensuring synchronous operation even when sharing PLL circuits.
3Reliability
If synchronization code is added to each data path, then data synchronization is achieved, but device complexity increases
Solution Approach 1:
The synchronization code serves multiple functions simultaneously: it acts as a timing reference, an alignment marker, and a synchronization signal. This multi-functionality reduces the need for separate synchronization mechanisms in each data path, thereby limiting the increase in device complexity while achieving reliable synchronization.
Data Source
AI summary
In an image capturing apparatus, a first output unit outputs a plurality of sets of first data obtained by adding a synchronization code to a pixel signal. A second output unit outputs a plurality of sets of second data obtained by adding the synchronization code to the pixel signal. A first correction unit corrects a shift in timing between the plurality of sets of first data output from the first output unit. A second correction unit corrects a shift in timing between the plurality of sets of second data output from the second output unit. A third correction unit corrects a shift in timing between the plurality of sets of first data that have been corrected by the first correction unit and the plurality of sets of second data that have been corrected by the second correction unit, based on the synchronization code.