Image Processing Chip With Digital Port Switching for USB-C and DP
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Solution Overview
Problem
Existing image processing chip architectures using USB Type-C connectors face challenges with signal quality and PCB area utilization due to the need for multiple lane-to-lane multiplexers, which result in poor signal quality and increased costs, and port-to-port multiplexers are limited in adapting four pairs of high-speed signal channels.
Innovation Solution
An image processing chip with built-in digital multiplexers that can distinguish between USB and DisplayPort signal channels, reducing the need for multiple multiplexers, thereby minimizing PCB area usage, costs, and signal penetration, while enabling arbitrary switching between multiple upstream and downstream facing ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple lane-to-lane multiplexers are used to achieve port-to-port switching, then switching functionality is achieved, but PCB area increases and signal quality deteriorates
Solution Approach 1:
The patent combines multiple lane-to-lane multiplexer functions into a single integrated port-to-port multiplexer chip. This consolidation integrates the switching logic and multiplexing functions that were previously distributed across multiple discrete components on the PCB, thereby reducing the overall PCB area while maintaining the required port-to-port switching functionality.
Solution Approach 2:
The port-to-port multiplexer chip acts as an intermediary device that directly connects multiple USB Type-C ports to a single DisplayPort interface. By placing the intelligence and switching logic within this intermediary chip rather than using multiple discrete multiplexers on the PCB, the solution reduces signal penetration through PCB layers and improves signal quality while achieving the desired switching capability.
2Adaptability or versatility
If multiple lane-to-lane multiplexers are used for port-to-port switching, then switching functionality is achieved, but signal quality deteriorates due to multiple PCB layer penetrations
Solution Approach 1:
The patent consolidates multiple discrete multiplexer functions into a single integrated port-to-port multiplexer chip. This integration reduces the number of times signals must penetrate through PCB layers by providing a dedicated switching path within the chip itself, thereby minimizing signal degradation and improving overall signal quality while maintaining the required switching functionality.
Solution Approach 2:
The port-to-port multiplexer chip serves as an intermediary that handles signal switching internally without requiring multiple PCB layer penetrations. By routing signals through this dedicated intermediary device rather than through multiple discrete multiplexers mounted on the PCB, the solution reduces signal interference and maintains better signal integrity.
3Area of stationary object
If port-to-port multiplexer is used to reduce PCB area, then PCB area is reduced, but the solution is limited to adapting multiple ports to a single port and cannot handle four pairs of high-speed signal channels
Solution Approach 1:
The patent enhances the port-to-port multiplexer chip with built-in digital multiplexers that enable it to handle four pairs of high-speed signal channels. This multi-functional design allows the single chip to not only perform port-to-port switching but also to actively or passively distinguish between USB signal channels and DP signal channels, making it versatile enough to process all four pairs of high-speed channels defined by the USB Type-C connector specification.
Solution Approach 2:
The patent incorporates digital multiplexing capabilities that change the operational parameters of the multiplexer chip. By using digital rather than purely analog switching mechanisms, the chip can actively or passively distinguish between different signal types (USB vs. DP) and properly route four pairs of high-speed signal channels, thereby expanding its adaptability while maintaining reduced PCB area usage.
Data Source
AI summary
An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.