Image Pickup Circuit Block Layout for Shared Counter A/D Conversion
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Solution Overview
Problem
Existing solid-state image pickup devices face challenges in reducing power consumption and maintaining image quality due to the need for multiple counters and the resulting increased circuit area and power consumption, as well as delays caused by wire resistance and capacity in shared counter configurations.
Innovation Solution
The implementation of an image pickup circuit with a single counter shared among multiple circuit blocks, where each block includes comparing elements and storage units that compare pixel signals with a slope signal and store count values, reducing the number of counters needed and minimizing delays through efficient signal processing and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a counter is provided for every column of pixels, then A/D conversion can be performed in parallel for each column, but the number of counters increases, leading to increased circuit area and power consumption
Solution Approach 1:
The pixel array is divided into multiple blocks, with each block containing a subset of columns. Each block has its own counter, allowing parallel processing within blocks while reducing the total number of counters compared to providing one counter per column across the entire array.
Solution Approach 2:
Instead of organizing counters in a single dimension (one per column), the patent introduces a two-dimensional organization by dividing the array into blocks. This block-based structure adds a spatial dimension to the counter distribution, enabling parallel processing while optimizing resource usage.
2Device complexity
If a single counter is shared among multiple columns, then the number of counters is reduced, but delays occur due to wire resistance and capacity affecting signal transmission
Solution Approach 1:
By segmenting the pixel array into multiple blocks, each with its own counter, the patent reduces the maximum distance that count signals must travel within a block. This segmentation minimizes the impact of wire resistance and capacity while still reducing the total number of counters compared to a per-column approach.
Solution Approach 2:
Each block is designed as a self-contained unit with local counters, ensuring that signal transmission distances are kept short and uniform within each block. This local organization maintains signal integrity while optimizing the overall counter distribution across the array.
3Productivity
If multiple counters are used for parallel processing, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent divides the pixel array into blocks and allocates counters to blocks rather than to individual columns. This segmentation enables parallel processing within blocks while significantly reducing the total number of counters, thereby lowering power consumption while maintaining acceptable processing speed.
Solution Approach 2:
Instead of providing full parallel processing capability for every column (excessive action), the patent implements partial parallel processing within blocks. This approach achieves sufficient processing speed for the application while avoiding the power consumption penalty of complete per-column parallelism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power consumption and circuit area while maintaining image quality by sharing a single counter among multiple columns, thereby addressing the limitations of previous technologies.
Implementation Method 1
The pixel array 22 is composed of a plurality of pixels arranged in a matrix... The individual pixels 22n (n=1, 2, . . . , N) photoelectrically convert the incident light, and output the pixel signal of a voltage corresponding to the light.
Implementation Method 2
The slope generating circuit 25 supplies a slope signal, whose voltage drops (or rises) at a constant slope from a predetermined initial voltage
Implementation Method 3
The comparators 261 to 26N compare the pixel signals supplied from the pixels 221 to 22N, and the slope signal supplied from the slope generating circuit 25
Implementation Method 4
The counters 271 to 27N count a predetermined clock signal on the basis of the comparative signals supplied from the comparators 261 to 26N
Data Source
AI summary
An image pickup circuit includes a plurality of circuit blocks. Each of the plurality of circuit blocks includes a plurality of comparing elements, a single counter, and a plurality of storage units. Each of the comparing elements compares a pixel signal supplied through a vertical signal line connected to vertically aligned pixels in a plurality of pixels arranged in a matrix, and a slope signal whose voltage is changed from an initial voltage at a constant slope. The counter counts an elapsed time since a voltage of the slope signal starts to change from the initial voltage. Each of the storage units stores a count value obtained by the counter in accordance with a comparison result of the comparator, the count value corresponding to an elapsed time until the voltage of the slope signal is changed from the initial voltage to a voltage coinciding with the pixel signal.