Image Processing Circuit With Multi-Path Output Timing Adjustment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing image sources fail to provide optimal image quality and playback fluency, and are unable to adapt to different formats required by various electronic apparatuses due to the absence of a suitable image processing mechanism.

Innovation Solution

An image processing circuit and method that includes an input interface, enhancement circuit, multiple processing paths, and timing control circuit to adjust output timing, allowing for image enhancement and separate processing paths to meet the requirements of different output interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single image processing path is used, then device complexity is reduced, but adaptability to different processing requirements deteriorates

Engineering Contradiction:
Improveprocessing path structureVSAvoidoutput timing adjustment
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The image processing circuit is divided into multiple independent processing paths (first image processing path and second image processing path), each capable of independent timing adjustment. This segmentation allows different timing configurations for different output interfaces while maintaining a unified overall structure, resolving the contradiction between device complexity and adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces dynamic timing adjustment mechanisms in each processing path, allowing the timing parameters to be flexibly changed according to different processing requirements. The first and second processing paths can independently adjust their timing parameters, providing adaptability without requiring a completely different system architecture for each scenario.

Inventive Principle:
Principle #15Dynamics

2Reliability

If separate image enhancement circuits are used for each processing path, then processing independence is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing independenceVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the image enhancement functionality into a single shared circuit that serves both processing paths. This shared image enhancement circuit processes images for both paths simultaneously, reducing device complexity while maintaining processing independence through the timing control circuit that directs the enhanced images to appropriate paths with different timing characteristics.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If timing adjustment is added to meet different processing requirements, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvetiming adjustment capabilityVSAvoidcontrol circuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The timing control circuit implements local timing adjustment within each processing path rather than requiring global timing control for the entire system. Each path (first and second image processing paths) has its own timing adjustment capability, allowing precise local optimization without overwhelming global complexity. This localized approach enables adaptability while keeping the control structure manageable.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12614258B2Image processing circuit and method having output timing adjustment mechanism
Publication Date: 2026.04.28 REALTEK SEMICON CORP
  • US12614258B2 patent drawing
  • US12614258B2 patent drawing
  • US12614258B2 patent drawing

AI summary

The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.